FPGA motherboard for 80386 CPU

[Rick C. Hodgin]

The 80386DX CPU had 132 pins:

80386DX and 80386SX pinouts:
http://www.rfwireless-world.com/images/80386-pin-diagram.jpg
https://image.slidesharecdn.com/salientfeatursof80386-140822084001-phpapp02/95/salient-featurs-of-80386-14-638.jpg?cb=1408709884

General architecture:
http://www.nptel.ac.in/courses/Webcourse-contents/IISc-BANG/Microprocessors%20and%20Microcontrollers/pdf/Teacher_Slides/mod8/M8L1.pdf

Of these pins on the DX variant:

32 pins -- data
30 pins -- address
4 pins -- byte enables in 32-bit writes
1 pin -- Read/write
1 pin -- Data/Control
1 pin -- Memory/IO
1 pin -- Bus mastering lock issued by CPU
1 pin -- Bus16 size (16-bit when asserted, normally 32-bit)
1 pin -- Next address (for pipelining)
1 pin -- Address valid signal
--
73 pins -- For basic I/O

3 pins -- Math-coprocessor support
1 pin -- Ready (or Wait, for bus cycles to complete)
2 pins -- Hold and Hold Acknowledge (for bus mastering)
2 pins -- Interrupt and Non-masktable Interrupt
--
8 pins -- General coordination with external peripherals

1 pin -- Reset
1 pin -- Double-pumped clock
--
2 pins -- System input

The rest of the pins are unused, go to VSS or VCC. This means that for a
full 80386 "motherboard" only 83 pins are required to fully support its
operation, 67 of which are address, data, and data type, leaving really
only 15 pins of complex operation for a state machine.

-----
Would anybody be able to help me create this 80386 motherboard using an
AMD Am386 CPU, which is a static CPU operating from 0 to 40 MHz? I would
like to get it working with a single-step operation for design validation,
and then to begin ramping it up.

I figure I'll have an area of ROM which the CPU boots to load, which is a
tiny real mode program, which begins computing something that can be exam-
ined by the FPGA to test successful operation. And then move on to more
complex operations, including a custom microkernel.

--
Rick C. Hodgin

 

[rickman]

Rick C. Hodgin wrote on 11/10/2017 10:35 AM:

The 80386DX CPU had 132 pins:

80386DX and 80386SX pinouts:
http://www.rfwireless-world.com/images/80386-pin-diagram.jpg
https://image.slidesharecdn.com/salientfeatursof80386-140822084001-phpapp02/95/salient-featurs-of-80386-14-638.jpg?cb=1408709884

General architecture:
http://www.nptel.ac.in/courses/Webcourse-contents/IISc-BANG/Microprocessors%20and%20Microcontrollers/pdf/Teacher_Slides/mod8/M8L1.pdf

Of these pins on the DX variant:

32 pins -- data
30 pins -- address
4 pins -- byte enables in 32-bit writes
1 pin -- Read/write
1 pin -- Data/Control
1 pin -- Memory/IO
1 pin -- Bus mastering lock issued by CPU
1 pin -- Bus16 size (16-bit when asserted, normally 32-bit)
1 pin -- Next address (for pipelining)
1 pin -- Address valid signal
--
73 pins -- For basic I/O

3 pins -- Math-coprocessor support
1 pin -- Ready (or Wait, for bus cycles to complete)
2 pins -- Hold and Hold Acknowledge (for bus mastering)
2 pins -- Interrupt and Non-masktable Interrupt
--
8 pins -- General coordination with external peripherals

1 pin -- Reset
1 pin -- Double-pumped clock
--
2 pins -- System input

The rest of the pins are unused, go to VSS or VCC. This means that for a
full 80386 "motherboard" only 83 pins are required to fully support its
operation, 67 of which are address, data, and data type, leaving really
only 15 pins of complex operation for a state machine.

-----
Would anybody be able to help me create this 80386 motherboard using an
AMD Am386 CPU, which is a static CPU operating from 0 to 40 MHz? I would
like to get it working with a single-step operation for design validation,
and then to begin ramping it up.

I figure I'll have an area of ROM which the CPU boots to load, which is a
tiny real mode program, which begins computing something that can be exam-
ined by the FPGA to test successful operation. And then move on to more
complex operations, including a custom microkernel.

I'm sure many here would be *able* to help you. The question you should be
asking is who would be *willing* to help you...

What parts are you having trouble with? Why do you need help exactly?

--

Rick C

Viewed the eclipse at Wintercrest Farms,
on the centerline of totality since 1998

 

[Rick C. Hodgin]

On Friday, November 10, 2017 at 2:46:34 PM UTC-5, rickman wrote:

Rick C. Hodgin wrote on 11/10/2017 10:35 AM:
The 80386DX CPU had 132 pins:

80386DX and 80386SX pinouts:
http://www.rfwireless-world.com/images/80386-pin-diagram.jpg
https://image.slidesharecdn.com/salientfeatursof80386-140822084001-phpapp02/95/salient-featurs-of-80386-14-638.jpg?cb=1408709884

General architecture:
http://www.nptel.ac.in/courses/Webcourse-contents/IISc-BANG/Microprocessors%20and%20Microcontrollers/pdf/Teacher_Slides/mod8/M8L1.pdf

Of these pins on the DX variant:

32 pins -- data
30 pins -- address
4 pins -- byte enables in 32-bit writes
1 pin -- Read/write
1 pin -- Data/Control
1 pin -- Memory/IO
1 pin -- Bus mastering lock issued by CPU
1 pin -- Bus16 size (16-bit when asserted, normally 32-bit)
1 pin -- Next address (for pipelining)
1 pin -- Address valid signal
--
73 pins -- For basic I/O

3 pins -- Math-coprocessor support
1 pin -- Ready (or Wait, for bus cycles to complete)
2 pins -- Hold and Hold Acknowledge (for bus mastering)
2 pins -- Interrupt and Non-masktable Interrupt
--
8 pins -- General coordination with external peripherals

1 pin -- Reset
1 pin -- Double-pumped clock
--
2 pins -- System input

The rest of the pins are unused, go to VSS or VCC. This means that for a
full 80386 "motherboard" only 83 pins are required to fully support its
operation, 67 of which are address, data, and data type, leaving really
only 15 pins of complex operation for a state machine.

-----
Would anybody be able to help me create this 80386 motherboard using an
AMD Am386 CPU, which is a static CPU operating from 0 to 40 MHz? I would
like to get it working with a single-step operation for design validation,
and then to begin ramping it up.

I figure I'll have an area of ROM which the CPU boots to load, which is a
tiny real mode program, which begins computing something that can be exam-
ined by the FPGA to test successful operation. And then move on to more
complex operations, including a custom microkernel.

I'm sure many here would be *able* to help you. The question you should be
asking is who would be *willing* to help you...

What parts are you having trouble with? Why do you need help exactly?

The 80386DX was a 5V part. My FPGA supports 3.3V, so I need some
kind of level shifter? I'll need to build a breakout board to route
through my existing 40-pin FPGA breakout ports (160 pins). So, do
I go with an online custom manufacturer? Buy materials and pattern
and etch my own board, soldering everything myself? Are there generic
sockets the Am386 would fit in which are already broken out?

I need help with the mechanics of Verilog. I know how I want things
to route, but the mechanics of the language confuse me. I don't
understand why at times I need registers, and other times I can
route wires. The assignments are confusing me, when to use <= and
when not to, etc.

I need basic help to get my feet off the ground.

--
Rick C. Hodgin

 

[rickman]

Rick C. Hodgin wrote on 11/10/2017 3:19 PM:

On Friday, November 10, 2017 at 2:46:34 PM UTC-5, rickman wrote:
Rick C. Hodgin wrote on 11/10/2017 10:35 AM:
The 80386DX CPU had 132 pins:

80386DX and 80386SX pinouts:
http://www.rfwireless-world.com/images/80386-pin-diagram.jpg
https://image.slidesharecdn.com/salientfeatursof80386-140822084001-phpapp02/95/salient-featurs-of-80386-14-638.jpg?cb=1408709884

General architecture:
http://www.nptel.ac.in/courses/Webcourse-contents/IISc-BANG/Microprocessors%20and%20Microcontrollers/pdf/Teacher_Slides/mod8/M8L1.pdf

Of these pins on the DX variant:

32 pins -- data
30 pins -- address
4 pins -- byte enables in 32-bit writes
1 pin -- Read/write
1 pin -- Data/Control
1 pin -- Memory/IO
1 pin -- Bus mastering lock issued by CPU
1 pin -- Bus16 size (16-bit when asserted, normally 32-bit)
1 pin -- Next address (for pipelining)
1 pin -- Address valid signal
--
73 pins -- For basic I/O

3 pins -- Math-coprocessor support
1 pin -- Ready (or Wait, for bus cycles to complete)
2 pins -- Hold and Hold Acknowledge (for bus mastering)
2 pins -- Interrupt and Non-masktable Interrupt
--
8 pins -- General coordination with external peripherals

1 pin -- Reset
1 pin -- Double-pumped clock
--
2 pins -- System input

The rest of the pins are unused, go to VSS or VCC. This means that for a
full 80386 "motherboard" only 83 pins are required to fully support its
operation, 67 of which are address, data, and data type, leaving really
only 15 pins of complex operation for a state machine.

-----
Would anybody be able to help me create this 80386 motherboard using an
AMD Am386 CPU, which is a static CPU operating from 0 to 40 MHz? I would
like to get it working with a single-step operation for design validation,
and then to begin ramping it up.

I figure I'll have an area of ROM which the CPU boots to load, which is a
tiny real mode program, which begins computing something that can be exam-
ined by the FPGA to test successful operation. And then move on to more
complex operations, including a custom microkernel.

I'm sure many here would be *able* to help you. The question you should be
asking is who would be *willing* to help you...

What parts are you having trouble with? Why do you need help exactly?

The 80386DX was a 5V part. My FPGA supports 3.3V, so I need some
kind of level shifter? I'll need to build a breakout board to route
through my existing 40-pin FPGA breakout ports (160 pins). So, do
I go with an online custom manufacturer? Buy materials and pattern
and etch my own board, soldering everything myself? Are there generic
sockets the Am386 would fit in which are already broken out?

I don't follow what you are saying here. What is a 40 pin breakout port?
Are you talking about connectors on an FPGA board? I don't understand your
goals, so I can't help you figure out what you need to do. Are you trying
to make a board that will plug into the existing socket on a 386 motherboard?

I need help with the mechanics of Verilog. I know how I want things
to route, but the mechanics of the language confuse me. I don't
understand why at times I need registers, and other times I can
route wires. The assignments are confusing me, when to use <= and
when not to, etc.

I'm not a Verilog guy so I can't help you with that. I'm more of a VHDL guy.


> I need basic help to get my feet off the ground.

What's wrong with keeping your feet on the ground?

We've had this conversation before. Every project starts with goals (user
requirements in a formal analysis) which need to be translated to design
requirements and finally detailed as an implementation. You tend to mix
those various levels without understanding you are doing that.

What are your goals exactly?

--

Rick C

Viewed the eclipse at Wintercrest Farms,
on the centerline of totality since 1998

 

Den fredag den 10. november 2017 kl. 21.20.02 UTC+1 skrev Rick C. Hodgin:

On Friday, November 10, 2017 at 2:46:34 PM UTC-5, rickman wrote:
Rick C. Hodgin wrote on 11/10/2017 10:35 AM:
The 80386DX CPU had 132 pins:

80386DX and 80386SX pinouts:
http://www.rfwireless-world.com/images/80386-pin-diagram.jpg
https://image.slidesharecdn.com/salientfeatursof80386-140822084001-phpapp02/95/salient-featurs-of-80386-14-638.jpg?cb=1408709884

General architecture:
http://www.nptel.ac.in/courses/Webcourse-contents/IISc-BANG/Microprocessors%20and%20Microcontrollers/pdf/Teacher_Slides/mod8/M8L1.pdf

Of these pins on the DX variant:

32 pins -- data
30 pins -- address
4 pins -- byte enables in 32-bit writes
1 pin -- Read/write
1 pin -- Data/Control
1 pin -- Memory/IO
1 pin -- Bus mastering lock issued by CPU
1 pin -- Bus16 size (16-bit when asserted, normally 32-bit)
1 pin -- Next address (for pipelining)
1 pin -- Address valid signal
--
73 pins -- For basic I/O

3 pins -- Math-coprocessor support
1 pin -- Ready (or Wait, for bus cycles to complete)
2 pins -- Hold and Hold Acknowledge (for bus mastering)
2 pins -- Interrupt and Non-masktable Interrupt
--
8 pins -- General coordination with external peripherals

1 pin -- Reset
1 pin -- Double-pumped clock
--
2 pins -- System input

The rest of the pins are unused, go to VSS or VCC. This means that for a
full 80386 "motherboard" only 83 pins are required to fully support its
operation, 67 of which are address, data, and data type, leaving really
only 15 pins of complex operation for a state machine.

-----
Would anybody be able to help me create this 80386 motherboard using an
AMD Am386 CPU, which is a static CPU operating from 0 to 40 MHz? I would
like to get it working with a single-step operation for design validation,
and then to begin ramping it up.

I figure I'll have an area of ROM which the CPU boots to load, which is a
tiny real mode program, which begins computing something that can be exam-
ined by the FPGA to test successful operation. And then move on to more
complex operations, including a custom microkernel.

I'm sure many here would be *able* to help you. The question you should be
asking is who would be *willing* to help you...

What parts are you having trouble with? Why do you need help exactly?

The 80386DX was a 5V part. My FPGA supports 3.3V, so I need some
kind of level shifter? I'll need to build a breakout board to route
through my existing 40-pin FPGA breakout ports (160 pins). So, do
I go with an online custom manufacturer? Buy materials and pattern
and etch my own board, soldering everything myself? Are there generic
sockets the Am386 would fit in which are already broken out?

I need help with the mechanics of Verilog. I know how I want things
to route, but the mechanics of the language confuse me. I don't
understand why at times I need registers, and other times I can
route wires. The assignments are confusing me, when to use <= and
when not to, etc.

then you should probably start with a basic verilog project with some blinking leds and not a giant hairball of a CISC cpu...

 

[Rick C. Hodgin]

On Friday, November 10, 2017 at 4:15:43 PM UTC-5, lasselangwad...@gmail.com wrote:

Den fredag den 10. november 2017 kl. 21.20.02 UTC+1 skrev Rick C. Hodgin:
On Friday, November 10, 2017 at 2:46:34 PM UTC-5, rickman wrote:
Rick C. Hodgin wrote on 11/10/2017 10:35 AM:
The 80386DX CPU had 132 pins:

80386DX and 80386SX pinouts:
http://www.rfwireless-world.com/images/80386-pin-diagram.jpg
https://image.slidesharecdn.com/salientfeatursof80386-140822084001-phpapp02/95/salient-featurs-of-80386-14-638.jpg?cb=1408709884

General architecture:
http://www.nptel.ac.in/courses/Webcourse-contents/IISc-BANG/Microprocessors%20and%20Microcontrollers/pdf/Teacher_Slides/mod8/M8L1.pdf

Of these pins on the DX variant:

32 pins -- data
30 pins -- address
4 pins -- byte enables in 32-bit writes
1 pin -- Read/write
1 pin -- Data/Control
1 pin -- Memory/IO
1 pin -- Bus mastering lock issued by CPU
1 pin -- Bus16 size (16-bit when asserted, normally 32-bit)
1 pin -- Next address (for pipelining)
1 pin -- Address valid signal
--
73 pins -- For basic I/O

3 pins -- Math-coprocessor support
1 pin -- Ready (or Wait, for bus cycles to complete)
2 pins -- Hold and Hold Acknowledge (for bus mastering)
2 pins -- Interrupt and Non-masktable Interrupt
--
8 pins -- General coordination with external peripherals

1 pin -- Reset
1 pin -- Double-pumped clock
--
2 pins -- System input

The rest of the pins are unused, go to VSS or VCC. This means that for a
full 80386 "motherboard" only 83 pins are required to fully support its
operation, 67 of which are address, data, and data type, leaving really
only 15 pins of complex operation for a state machine.

-----
Would anybody be able to help me create this 80386 motherboard using an
AMD Am386 CPU, which is a static CPU operating from 0 to 40 MHz? I would
like to get it working with a single-step operation for design validation,
and then to begin ramping it up.

I figure I'll have an area of ROM which the CPU boots to load, which is a
tiny real mode program, which begins computing something that can be exam-
ined by the FPGA to test successful operation. And then move on to more
complex operations, including a custom microkernel.

I'm sure many here would be *able* to help you. The question you should be
asking is who would be *willing* to help you...

What parts are you having trouble with? Why do you need help exactly?

The 80386DX was a 5V part. My FPGA supports 3.3V, so I need some
kind of level shifter? I'll need to build a breakout board to route
through my existing 40-pin FPGA breakout ports (160 pins). So, do
I go with an online custom manufacturer? Buy materials and pattern
and etch my own board, soldering everything myself? Are there generic
sockets the Am386 would fit in which are already broken out?

I need help with the mechanics of Verilog. I know how I want things
to route, but the mechanics of the language confuse me. I don't
understand why at times I need registers, and other times I can
route wires. The assignments are confusing me, when to use <= and
when not to, etc.

then you should probably start with a basic verilog project with some blinking leds and not a giant hairball of a CISC cpu...

I've done that. I've made the KITT car red light thing. I've
responded to buttons. I've debounced inputs. An on Arduino,
which is basically C code, I've made tone generators, sent output
on a clock to a remote device on 18 pins, etc.

I know what I'm doing conceptually. I need help in the mechanics
in Verilog, and on some practical decisions.

BTW, your reply made me LOL when I got to the "hairball" part.

--
Rick C. Hodgin

 

[Rick C. Hodgin]

On Friday, November 10, 2017 at 4:11:44 PM UTC-5, rickman wrote:

What is a 40 pin breakout port?
Are you talking about connectors on an FPGA board?

The FPGA uses a high density 160-pin connection. You can buy an
add-on board which takes the high-density connection and breaks
it out to 4x 40-pin connectors (like IDE cables).

Are you trying
to make a board that will plug into the existing socket
on a 386 motherboard?

I'm trying to create a board an Am386 CPU will plug in to, which
then makes my FPGA its motherboard. I will be the north bridge
(memory and high speed I/O like graphics) and south bridge (low
speed I/O like keyboard, mouse, timer, etc).

We've had this conversation before. Every project starts with goals (user
requirements in a formal analysis) which need to be translated to design
requirements and finally detailed as an implementation. You tend to mix
those various levels without understanding you are doing that.

I know what I want. I tend to work in my head more than in formal
writings.

> What are your goals exactly?

(1) Get the board designed physically, and ordered or built.
(2) Assemble the board.
(3) Write the Verilog code to feed and respond to the CPU's needs.
(4) Write basic software to test and debug the design.
(5) Write real hardware for video, sound, network, keyboard, mouse,
etc., to create a little 80386-based system.

Thank you,
Rick C. Hodgin

 

[rickman]

Rick C. Hodgin wrote on 11/10/2017 5:14 PM:

On Friday, November 10, 2017 at 4:11:44 PM UTC-5, rickman wrote:
What is a 40 pin breakout port?
Are you talking about connectors on an FPGA board?

The FPGA uses a high density 160-pin connection. You can buy an
add-on board which takes the high-density connection and breaks
it out to 4x 40-pin connectors (like IDE cables).

Are you trying
to make a board that will plug into the existing socket
on a 386 motherboard?

I'm trying to create a board an Am386 CPU will plug in to, which
then makes my FPGA its motherboard. I will be the north bridge
(memory and high speed I/O like graphics) and south bridge (low
speed I/O like keyboard, mouse, timer, etc).

We've had this conversation before. Every project starts with goals (user
requirements in a formal analysis) which need to be translated to design
requirements and finally detailed as an implementation. You tend to mix
those various levels without understanding you are doing that.

I know what I want. I tend to work in my head more than in formal
writings.

If you want to work with people, they can't see what's in your head. You
need to write stuff down to get help.

What are your goals exactly?

(1) Get the board designed physically, and ordered or built.

You need to define the board a lot better.

(2) Assemble the board.
(3) Write the Verilog code to feed and respond to the CPU's needs.

That will require the FPGA either allow the CPU access to a memory device or
some other way serve up data from RAM and/or ROM. Do you know what you want
for that?

What other types of I/O do you intend to provide? Are you familiar with the
entire interface of the 386 CPU? You will need to know every detail. To
design the equivalent of a motherboard you would do well to find a 386 PC/AT
technical reference manual or other schematic for a motherboard. They used
TTL logic and you can easily implement that in the FPGA.

(4) Write basic software to test and debug the design.
(5) Write real hardware for video, sound, network, keyboard, mouse,
etc., to create a little 80386-based system.

So you want a full computer in an FPGA other than the 386 CPU? You will
also need a BIOS which is not open source... unless someone has an open
source BIOS... I don't recall hearing of one.

So where are the parts you need help with?

--

Rick C

Viewed the eclipse at Wintercrest Farms,
on the centerline of totality since 1998

 

[Rick C. Hodgin]

On Friday, November 10, 2017 at 6:31:25 PM UTC-5, rickman wrote:

Rick C. Hodgin wrote on 11/10/2017 5:14 PM:
On Friday, November 10, 2017 at 4:11:44 PM UTC-5, rickman wrote:
What are your goals exactly?
(1) Get the board designed physically, and ordered or built.
You need to define the board a lot better.

As I see it, the CPU is a black box. I connect wires to it and
give it power and turn things on and off, and observe it turning
things on and off, all by protocol, and it doesn't need anything
else.

I route all pins to appropriate I/O on the FPGA, or Vcc, and then
I need to have simulated ROM at the boot address, which simulates
BIOS. And I just read the Am386 was a CMOS 3.3V part, so that removes
level shifters.

Since I am the motherboard, all my BIOS would need to do is setup
interrupt vectors for CPU-issued interrupts (0x0 through 0x1f),
and run some software that does something I have control over.

First thing I need to do is get help on board design and components.
I'm thinking a socket (Package: PGA-132) with pins routed to the
mated 40-pin breakouts I would assign on my FPGA. Of the 160 pins,
only so many are GPIO, so I would have that limitation on design.

I think I could do all that, but there are things I don't know.
Will I need capacitors? Resistors? Some kind of something to handle
electrical oddities? If not, then I assume making trace lines equal
is important, but not greatly at only 40 MHz.

On the FPGA, it would route address and data pins to logic identifying
memory and I/O, and read / write, responding appropriately, routing
certain memory to emulated ROM, the rest to on-FPGA SRAM emulating
DRAM.

It seems a simple physical design. Moderately complex logically.
And very exciting.

--
Rick C. Hodgin

 

[rickman]

Rick C. Hodgin wrote on 11/10/2017 6:59 PM:

On Friday, November 10, 2017 at 6:31:25 PM UTC-5, rickman wrote:
Rick C. Hodgin wrote on 11/10/2017 5:14 PM:
On Friday, November 10, 2017 at 4:11:44 PM UTC-5, rickman wrote:
What are your goals exactly?
(1) Get the board designed physically, and ordered or built.
You need to define the board a lot better.

As I see it, the CPU is a black box. I connect wires to it and
give it power and turn things on and off, and observe it turning
things on and off, all by protocol, and it doesn't need anything
else.

Everything is a black box in that sense. The "protocol" is the part you
need to understand in detail.

I route all pins to appropriate I/O on the FPGA, or Vcc, and then
I need to have simulated ROM at the boot address, which simulates
BIOS. And I just read the Am386 was a CMOS 3.3V part, so that removes
level shifters.

I can't find anything that says it was 3.3 volt. Where did you read this?

Since I am the motherboard, all my BIOS would need to do is setup
interrupt vectors for CPU-issued interrupts (0x0 through 0x1f),
and run some software that does something I have control over.

Yes, if you don't plan to run it as a PC, but have you figured out any of this?

First thing I need to do is get help on board design and components.
I'm thinking a socket (Package: PGA-132) with pins routed to the
mated 40-pin breakouts I would assign on my FPGA. Of the 160 pins,
only so many are GPIO, so I would have that limitation on design.

Board design is not as hard at 40 MHz as at 100's of MHz, but you still need
to know something about signal integrity. If not sometimes the voltages
will bounce and jitter and so look like the wrong voltage when sampled and
clocks can bounce and double clock on a single edge. This is *very*
important stuff to know.

I think I could do all that, but there are things I don't know.
Will I need capacitors? Resistors? Some kind of something to handle
electrical oddities? If not, then I assume making trace lines equal
is important, but not greatly at only 40 MHz.

If you are asking questions at this level, you will not be able to design a
board that will work. You need to learn basic electronics. What do you
know about electronics?

On the FPGA, it would route address and data pins to logic identifying
memory and I/O, and read / write, responding appropriately, routing
certain memory to emulated ROM, the rest to on-FPGA SRAM emulating
DRAM.

It seems a simple physical design. Moderately complex logically.
And very exciting.

I think you don't know enough to understand the problems involved in what
you are trying to do. For one, trying to ship signal lines through two
connectors, three boards and many inches of signal trace could result in
severe signal integrity problems. This is stuff I have to pay attention to
on one board with no connectors and fairly short signal traces.

--

Rick C

Viewed the eclipse at Wintercrest Farms,
on the centerline of totality since 1998

 

[Rick C. Hodgin]

On Friday, November 10, 2017 at 10:16:03 PM UTC-5, rickman wrote:

Rick C. Hodgin wrote on 11/10/2017 6:59 PM:
And I just read the Am386 was a CMOS 3.3V part, so that removes
level shifters.

I can't find anything that says it was 3.3 volt. Where did you read this?

Wikipedia:

https://en.m.wikipedia.org/wiki/Intel_80386

"The AMD Am386SX and Am386DX were almost exact clones of the
80386SX and 80386DX. Legal disputes caused production delays
for several years, but AMD's 40 MHz part eventually became
very popular with computer enthusiasts as a low-cost and
low-power alternative to the 25 MHz 486SX. The power draw was
further reduced in the "notebook models" (Am386 DXL/SXL/DXLV/
SXLV), which could operate with 3.3 V and were implemented in
fully static CMOS circuitry."

I do not find the same reference here or here:

http://www.cpu-world.com/CPUs/80386/MANUF-AMD.html
https://en.m.wikipedia.org/wiki/Am386

But I do find this:

AMD Am386DE-25KC
25 MHz
3-5 V
0.32-1.05 Watt
132-pin PQFP

So it might be this 25 MHz DE part.

--
Rick C. Hodgin

 

[Rick C. Hodgin]

On Friday, November 10, 2017 at 11:16:24 PM UTC-5, Rick C. Hodgin wrote:

On Friday, November 10, 2017 at 10:16:03 PM UTC-5, rickman wrote:
Rick C. Hodgin wrote on 11/10/2017 6:59 PM:
And I just read the Am386 was a CMOS 3.3V part, so that removes
level shifters.

I can't find anything that says it was 3.3 volt. Where did you read this?

Wikipedia:

https://en.m.wikipedia.org/wiki/Intel_80386

"The AMD Am386SX and Am386DX were almost exact clones of the
80386SX and 80386DX. Legal disputes caused production delays
for several years, but AMD's 40 MHz part eventually became
very popular with computer enthusiasts as a low-cost and
low-power alternative to the 25 MHz 486SX. The power draw was
further reduced in the "notebook models" (Am386 DXL/SXL/DXLV/
SXLV), which could operate with 3.3 V and were implemented in
fully static CMOS circuitry."

I do not find the same reference here or here:

http://www.cpu-world.com/CPUs/80386/MANUF-AMD.html
https://en.m.wikipedia.org/wiki/Am386

But I do find this:

AMD Am386DE-25KC
25 MHz
3-5 V
0.32-1.05 Watt
132-pin PQFP

So it might be this 25 MHz DE part.

Other references:

https://books.google.com/books?id=FeIuiOQN-nEC&pg=PT279&lpg=PT279
https://en.wikichip.org/wiki/File:Am386_Microprocessors_for_Personal_Computers_(1992).pdf

The PDF refers to an AMD document number #17028 for their 3V Am386.

--
Rick C. Hodgin

 

Den fredag den 10. november 2017 kl. 23.03.06 UTC+1 skrev Rick C. Hodgin:

On Friday, November 10, 2017 at 4:15:43 PM UTC-5, lasselangwad...@gmail.com wrote:
Den fredag den 10. november 2017 kl. 21.20.02 UTC+1 skrev Rick C. Hodgin:
On Friday, November 10, 2017 at 2:46:34 PM UTC-5, rickman wrote:
Rick C. Hodgin wrote on 11/10/2017 10:35 AM:
The 80386DX CPU had 132 pins:

80386DX and 80386SX pinouts:
http://www.rfwireless-world.com/images/80386-pin-diagram.jpg
https://image.slidesharecdn.com/salientfeatursof80386-140822084001-phpapp02/95/salient-featurs-of-80386-14-638.jpg?cb=1408709884

General architecture:
http://www.nptel.ac.in/courses/Webcourse-contents/IISc-BANG/Microprocessors%20and%20Microcontrollers/pdf/Teacher_Slides/mod8/M8L1.pdf

Of these pins on the DX variant:

32 pins -- data
30 pins -- address
4 pins -- byte enables in 32-bit writes
1 pin -- Read/write
1 pin -- Data/Control
1 pin -- Memory/IO
1 pin -- Bus mastering lock issued by CPU
1 pin -- Bus16 size (16-bit when asserted, normally 32-bit)
1 pin -- Next address (for pipelining)
1 pin -- Address valid signal
--
73 pins -- For basic I/O

3 pins -- Math-coprocessor support
1 pin -- Ready (or Wait, for bus cycles to complete)
2 pins -- Hold and Hold Acknowledge (for bus mastering)
2 pins -- Interrupt and Non-masktable Interrupt
--
8 pins -- General coordination with external peripherals

1 pin -- Reset
1 pin -- Double-pumped clock
--
2 pins -- System input

The rest of the pins are unused, go to VSS or VCC. This means that for a
full 80386 "motherboard" only 83 pins are required to fully support its
operation, 67 of which are address, data, and data type, leaving really
only 15 pins of complex operation for a state machine.

-----
Would anybody be able to help me create this 80386 motherboard using an
AMD Am386 CPU, which is a static CPU operating from 0 to 40 MHz? I would
like to get it working with a single-step operation for design validation,
and then to begin ramping it up.

I figure I'll have an area of ROM which the CPU boots to load, which is a
tiny real mode program, which begins computing something that can be exam-
ined by the FPGA to test successful operation. And then move on to more
complex operations, including a custom microkernel.

I'm sure many here would be *able* to help you. The question you should be
asking is who would be *willing* to help you...

What parts are you having trouble with? Why do you need help exactly?

The 80386DX was a 5V part. My FPGA supports 3.3V, so I need some
kind of level shifter? I'll need to build a breakout board to route
through my existing 40-pin FPGA breakout ports (160 pins). So, do
I go with an online custom manufacturer? Buy materials and pattern
and etch my own board, soldering everything myself? Are there generic
sockets the Am386 would fit in which are already broken out?

I need help with the mechanics of Verilog. I know how I want things
to route, but the mechanics of the language confuse me. I don't
understand why at times I need registers, and other times I can
route wires. The assignments are confusing me, when to use <= and
when not to, etc.

then you should probably start with a basic verilog project with some blinking leds and not a giant hairball of a CISC cpu...

I've done that. I've made the KITT car red light thing. I've
responded to buttons. I've debounced inputs. An on Arduino,
which is basically C code, I've made tone generators, sent output
on a clock to a remote device on 18 pins, etc.

any of that in verilog?

 

[Rick C. Hodgin]

On Monday, November 13, 2017 at 11:28:09 AM UTC-5, lasselangwad...@gmail.com wrote:

Den fredag den 10. november 2017 kl. 23.03.06 UTC+1 skrev Rick C. Hodgin:
then you should probably start with a basic verilog project with some blinking leds and not a giant hairball of a CISC cpu...

I've done that. I've made the KITT car red light thing. I've
responded to buttons. I've debounced inputs. An on Arduino,
which is basically C code, I've made tone generators, sent output
on a clock to a remote device on 18 pins, etc.

any of that in verilog?

Yes. Using Lattice's Diamond software on a Lattice XP2 Brevia board:

http://www.latticesemi.com/Products/FPGAandCPLD/LatticeXP2.aspx
http://www.latticesemi.com/~/media/LatticeSemi/Images/ProductImages/DevelopmentKitsAndBoards/XP2_Brevia/LatticeXP2%20Brevia2%20Development%20Kit_Front.png

I've also worked on an Altera board, which is what I'd be using for
this project:

Cyclone V GX Starter Kit
https://www.digikey.com/product-detail/en/P0150/P0150-ND/4437934

I have this breakout board HSMC to GPIO, yielding 120 pins, plus another
40 pins which are on the GX Starter Kit board:

https://www.digikey.com/product-detail/en/terasic-inc/P0033/P0033-ND/2003485

I wouldn't mind building a board which plugs directly in to the HSMC
port so that it has no cables, fewer connections. But, those are
the things I don't know about the hardware end of it. Logically, I
know I need to have this high and this low, and so on, and digitally
it would all work, but to transfer that digital logic to real analog
hardware ... I don't have any experience on it, apart from reading
many many many things about it.

--
Rick C. Hodgin

 

[Rick C. Hodgin]

Direct link for Lattice XP2 Brevia2 board:

http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/LatticeXP2Brevia2DevelopmentKit.aspx

--
Rick C. Hodgin

 

Den mandag den 13. november 2017 kl. 17.49.15 UTC+1 skrev Rick C. Hodgin:

On Monday, November 13, 2017 at 11:28:09 AM UTC-5, lasselangwad...@gmail.com wrote:
Den fredag den 10. november 2017 kl. 23.03.06 UTC+1 skrev Rick C. Hodgin:
then you should probably start with a basic verilog project with some blinking leds and not a giant hairball of a CISC cpu...

I've done that. I've made the KITT car red light thing. I've
responded to buttons. I've debounced inputs. An on Arduino,
which is basically C code, I've made tone generators, sent output
on a clock to a remote device on 18 pins, etc.

any of that in verilog?

Yes. Using Lattice's Diamond software on a Lattice XP2 Brevia board:

writing verilog or copy-pasting verilog ?

anyway, 99% of such a project will be done in a simulator

 

[Rick C. Hodgin]

On Monday, November 13, 2017 at 2:47:48 PM UTC-5, lasselangwad...@gmail.com wrote:

Den mandag den 13. november 2017 kl. 17.49.15 UTC+1 skrev Rick C. Hodgin:
On Monday, November 13, 2017 at 11:28:09 AM UTC-5, lasselangwad...@gmail.com wrote:
Den fredag den 10. november 2017 kl. 23.03.06 UTC+1 skrev Rick C. Hodgin:
then you should probably start with a basic verilog project with some blinking leds and not a giant hairball of a CISC cpu...

I've done that. I've made the KITT car red light thing. I've
responded to buttons. I've debounced inputs. An on Arduino,
which is basically C code, I've made tone generators, sent output
on a clock to a remote device on 18 pins, etc.

any of that in verilog?

Yes. Using Lattice's Diamond software on a Lattice XP2 Brevia board:

writing verilog or copy-pasting verilog ?

Writing Verilog. I've also written a CPU core that synthesized in
Altera's Quartus II software, but I never debugged it and I have no
idea if it actually works:

http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie1/oppie1.v

http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie1/debo-1-actual.png

http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie-1.png

> anyway, 99% of such a project will be done in a simulator

That would be great. How do I do it? What tools are available for
the Alter Cyclone V GX Starter Kit toolset?

--
Rick C. Hodgin

 

Den mandag den 13. november 2017 kl. 20.54.12 UTC+1 skrev Rick C. Hodgin:

On Monday, November 13, 2017 at 2:47:48 PM UTC-5, lasselangwad...@gmail.com wrote:
Den mandag den 13. november 2017 kl. 17.49.15 UTC+1 skrev Rick C. Hodgin:
On Monday, November 13, 2017 at 11:28:09 AM UTC-5, lasselangwad...@gmail.com wrote:
Den fredag den 10. november 2017 kl. 23.03.06 UTC+1 skrev Rick C. Hodgin:
then you should probably start with a basic verilog project with some blinking leds and not a giant hairball of a CISC cpu...

I've done that. I've made the KITT car red light thing. I've
responded to buttons. I've debounced inputs. An on Arduino,
which is basically C code, I've made tone generators, sent output
on a clock to a remote device on 18 pins, etc.

any of that in verilog?

Yes. Using Lattice's Diamond software on a Lattice XP2 Brevia board:

writing verilog or copy-pasting verilog ?

Writing Verilog. I've also written a CPU core that synthesized in
Altera's Quartus II software, but I never debugged it and I have no
idea if it actually works:

http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie1/oppie1.v

http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie1/debo-1-actual.png

http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie-1.png

anyway, 99% of such a project will be done in a simulator

That would be great. How do I do it? What tools are available for
the Alter Cyclone V GX Starter Kit toolset?

what's wrong with icarus iverilog? no point in looking at specific boards or fpgas until you have it working in a simulator

 

[Rick C. Hodgin]

On Monday, November 13, 2017 at 3:06:44 PM UTC-5, lasselangwad...@gmail.com wrote:

Den mandag den 13. november 2017 kl. 20.54.12 UTC+1 skrev Rick C. Hodgin:
On Monday, November 13, 2017 at 2:47:48 PM UTC-5, lasselangwad...@gmail.com wrote:
Den mandag den 13. november 2017 kl. 17.49.15 UTC+1 skrev Rick C. Hodgin:
writing verilog or copy-pasting verilog ?

Writing Verilog. I've also written a CPU core that synthesized in
Altera's Quartus II software, but I never debugged it and I have no
idea if it actually works:

http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie1/oppie1.v

http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie1/debo-1-actual.png

http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie-1.png

anyway, 99% of such a project will be done in a simulator

That would be great. How do I do it? What tools are available for
the Alter Cyclone V GX Starter Kit toolset?

what's wrong with icarus iverilog? no point in looking at specific boards or fpgas until you have it working in a simulator

I've found the tools clunky. I want to see some kind of visualization
like this:

http://www.visual6502.org/JSSim/index.html

Which produces information on runtime like this:

http://www.visual6502.org/JSSim/expert.html

And produces some kind of output like this:

(click the "Trace More" button many times)

-----
The reason I stopped working in Verilog was because I found it textual
and confusing. I had intended to write my Logician tool, which would
be a Blender node-like arrangement of hardware, allowing me to sample
all data lines, and visualize it as with the 6502 visualization.

Blender Node Editor (at 1:18 and after):
https://www.youtube.com/watch?v=sc-ptGft9Vk&t=1m18s

I haven't had time to do it yet, but there must be some tool closer
to that out there. If not, that's where we should start (writing
that tool for people to use).

--
Rick C. Hodgin

 

[Rick C. Hodgin]

On Friday, November 10, 2017 at 10:35:44 AM UTC-5, Rick C. Hodgin wrote:

The 80386DX CPU had 132 pins:

80386DX and 80386SX pinouts:
http://www.rfwireless-world.com/images/80386-pin-diagram.jpg
https://image.slidesharecdn.com/salientfeatursof80386-140822084001-phpapp02/95/salient-featurs-of-80386-14-638.jpg?cb=1408709884

General architecture:
http://www.nptel.ac.in/courses/Webcourse-contents/IISc-BANG/Microprocessors%20and%20Microcontrollers/pdf/Teacher_Slides/mod8/M8L1.pdf

Of these pins on the DX variant:

32 pins -- data
30 pins -- address
4 pins -- byte enables in 32-bit writes
1 pin -- Read/write
1 pin -- Data/Control
1 pin -- Memory/IO
1 pin -- Bus mastering lock issued by CPU
1 pin -- Bus16 size (16-bit when asserted, normally 32-bit)
1 pin -- Next address (for pipelining)
1 pin -- Address valid signal
--
73 pins -- For basic I/O

3 pins -- Math-coprocessor support
1 pin -- Ready (or Wait, for bus cycles to complete)
2 pins -- Hold and Hold Acknowledge (for bus mastering)
2 pins -- Interrupt and Non-masktable Interrupt
--
8 pins -- General coordination with external peripherals

1 pin -- Reset
1 pin -- Double-pumped clock
--
2 pins -- System input

The rest of the pins are unused, go to VSS or VCC. This means that for a
full 80386 "motherboard" only 83 pins are required to fully support its
operation, 67 of which are address, data, and data type, leaving really
only 15 pins of complex operation for a state machine.

-----
Would anybody be able to help me create this 80386 motherboard using an
AMD Am386 CPU, which is a static CPU operating from 0 to 40 MHz? I would
like to get it working with a single-step operation for design validation,
and then to begin ramping it up.

I figure I'll have an area of ROM which the CPU boots to load, which is a
tiny real mode program, which begins computing something that can be exam-
ined by the FPGA to test successful operation. And then move on to more
complex operations, including a custom microkernel.

Now that the intrusion appears to be over, would anybody like to help me
in preparation for this project?

Specifically, I'd like some help in guiding me toward the type of board
and sockets I'll need. I think I know what to do, but without someone
to say "yay" or "nay" I'm just guessing.

It will need a 132-pin PGA, a custom board which connects into the
three parallel 40-pin adapter board I have for my FPGA. In that way,
the 80386 chip will ride right above the FPGA, with traversing the main
40-pin-to-FPGA connection, and the 80386 board-to-40-pin connection.

80386
=========
|||||||||
===========================
|| || || <=== 3x 40-pin
=======================
|||| <=== Proprietary 120+pin adapter
=====[ FPGA ]==================

The FPGA I have is about 6" square, with the adapter board being about
2" x 3". The custom board I'll build will be about 3" x 3". The total
distance from FPGA to CPU will be about 9".

The Am386 CPU I plan to use is a static part able to run between 0 MHz
and 40 MHz inclusive. I plan to run around 1 MHz to start.

Please offer any advice. Thank you.

--
Rick C. Hodgin