FPGA minimum operating frequencies

[Nitin Chandrachoodan]

Hello,

I was wondering if there were any *lower* limits on the clock
frequency that can be used to clock FPGAs (in particular the Xilinx
Virtex II : XC2V3000). I know there are certain kinds of high speed
logic families using precharge-discharge operation, where the leakage
sets a lower limit on operating speed. Is there such a limit for these
FPGAs, and if so, what is it (ballpark figures are fine).

Thanks,

Nitin

 

[Austin Lesea]

All,

Good answers, and they are correct.

All static, no precharge tricks.

You can go to 1 milli-hertz if you like.

Austin

Nitin Chandrachoodan wrote:

Hello,

I was wondering if there were any *lower* limits on the clock
frequency that can be used to clock FPGAs (in particular the Xilinx
Virtex II : XC2V3000). I know there are certain kinds of high speed
logic families using precharge-discharge operation, where the leakage
sets a lower limit on operating speed. Is there such a limit for these
FPGAs, and if so, what is it (ballpark figures are fine).

Thanks,

Nitin

 

[WIlfredo Falcón]

Hello, <BR>
In which reports of time can I see the maximum frequency or haw can I to calculate it?. I am working with ISE 5.1i and for the synthesis I use xst. <p>Thanks, <BR>
Falcón.