FPGA & handling reset of a logic block while running

Hello,

In a current FPGA-based design, I have a sub-block whose synchronous
outputs drive some logic such as counters & flip-flops(external to
the sub-block but internal to the FPGA). The current design has the
sub-block synchronously enabled when it needs to be used and
synchronously disabled when it does not need to be used.

When the block is de-selected (going from enabled to disabled), I
would like the sub-block's flip-flops to be reset, so the next time
the block is enabled, the outputs are in a known state.

My question:

Is it safe to use a synchronous reset signal which is high for one
system clock cycle to drive the async reset on the flip-flops of my
sub-block?

Note: The sub-block flip-flops are synchronously disabled before being
reset by the synchronous reset signal, so I am not creating a
setup/hold time problem with the sub-block FFs.

My real concern is about violating the setup & hold time on the
flip-flops the sub-block drives. My thinking is that even though the
reset signal is synchronous, the sync. reset signal will probably not
be distributed via a low-skew line (aka global signal) and I could
potentially have a far sub-block flip-flop not reset by the time the
clock comes around, and thus I clober a flip-flop which is driven by a
s-b FF.

If driving the async. reset on the FFs is a bad idea, my other
approach was to take each DFF of the sub-block and update it to
include a 2-input AND gate on the input. One input to the AND2 gets
the original D-input signal while the second input gets a NOTed
SCLR(active high), so I create a synchronous clearable DFF.

I would appreciate comments, suggestions, etc.

Jay

 

[John_H]

Since this is the fpga newsgroup, not the ASIC folks....

Synchronous resets used directly in your design are great to use. The
timing analysis knows when sync resets use synchronous resources. Using a
synchronous signal to asynchronously reset is problematic but - after a few
incorrect tries - you can probably apply proper constraints to make them
work.

Some FPGAs have dedicated set/reset resources that can be either synchronous
or asynchronous. Other FPGAs have some of their logic configurations design
to use a synchronous clear applicable in the particular configuration.

Often adding a single additional input - in the form of the synchronous
reset - keeps the logic within the LUT or LE that was originally produced.
The performance reduction due to synchronous resets can be pretty minor -
often not an issue.

- John_H


<se10110@yahoo.com> wrote in message
news:96922c52.0311070357.7493b7c4@posting.google.com...

Hello,

In a current FPGA-based design, I have a sub-block whose synchronous
outputs drive some logic such as counters & flip-flops(external to
the sub-block but internal to the FPGA). The current design has the
sub-block synchronously enabled when it needs to be used and
synchronously disabled when it does not need to be used.

When the block is de-selected (going from enabled to disabled), I
would like the sub-block's flip-flops to be reset, so the next time
the block is enabled, the outputs are in a known state.

My question:

Is it safe to use a synchronous reset signal which is high for one
system clock cycle to drive the async reset on the flip-flops of my
sub-block?

Note: The sub-block flip-flops are synchronously disabled before being
reset by the synchronous reset signal, so I am not creating a
setup/hold time problem with the sub-block FFs.

My real concern is about violating the setup & hold time on the
flip-flops the sub-block drives. My thinking is that even though the
reset signal is synchronous, the sync. reset signal will probably not
be distributed via a low-skew line (aka global signal) and I could
potentially have a far sub-block flip-flop not reset by the time the
clock comes around, and thus I clober a flip-flop which is driven by a
s-b FF.

If driving the async. reset on the FFs is a bad idea, my other
approach was to take each DFF of the sub-block and update it to
include a 2-input AND gate on the input. One input to the AND2 gets
the original D-input signal while the second input gets a NOTed
SCLR(active high), so I create a synchronous clearable DFF.

I would appreciate comments, suggestions, etc.

Jay

 

[Mike Treseler]

se10110@yahoo.com wrote:

My real concern is about violating the setup & hold time on the
flip-flops the sub-block drives. My thinking is that even though the
reset signal is synchronous, the sync. reset signal will probably not
be distributed via a low-skew line

True. You wouldn't want to waste one for a single connection.

If driving the async. reset on the FFs is a bad idea, my other
approach was to take each DFF of the sub-block and update it to
include a 2-input AND gate on the input. One input to the AND2 gets
the original D-input signal while the second input gets a NOTed
SCLR(active high), so I create a synchronous clearable DFF.

Yes. Do that.

-- Mike Treseler