FPGA FIFO MAX data speed

[markc]

hi, guys:

i'm designing a fifo using XILINX FPGA V6. the fifo will be used t
transport data between ARM11(OR POWERPC) and TI DSP 6474. i know it'
related to the bus clock of both side, but how to calculate the max dat
rate that can be transferred.
can anyone tell me how?
thanks!

markc



---------------------------------------
Posted through http://www.FPGARelated.com

 

[Mawa_fugo]

On Jun 14, 6:11 am, "markc" <yuzhe_zhang@n_o_s_p_a_m.hotmail.com>
wrote:

hi, guys:

i'm designing a fifo using XILINX FPGA V6. the fifo will be used to
transport data between ARM11(OR POWERPC) and TI DSP 6474. i know it's
related to the bus clock of both side, but how to calculate the max data
rate that can be transferred.
can anyone tell me how?
thanks!

markc

---------------------------------------
Posted throughhttp://www.FPGARelated.com

Usually the max speed is slower one

Let say, you can make $10,000 each month,..but your spouse can spend
max $6,666 per 30 days

so the max you can give her (via the FIFO mail box) is $6,666/month...
because if you give her more than that she will give $$$ to someone
else

 

[Mike Young]

On 06/14/2012 06:11 AM, markc wrote:

hi, guys:

i'm designing a fifo using XILINX FPGA V6. the fifo will be used to
transport data between ARM11(OR POWERPC) and TI DSP 6474. i know it's
related to the bus clock of both side, but how to calculate the max data
rate that can be transferred.
can anyone tell me how?
thanks!

markc

The various time values are tabulated in the switching characteristics
section of the device data sheet. Their descriptions are in the device
user guide. Both documents are available at the Xilinx website.