FPGA Editor and Xilinx ISE 5.1i

[Santi]

Hi all!

I'm trying to make a hard macro of a design and I got that error:

FATAL_ERROR:Ncd:basncmacrodef.c:1466:1.19.2.1 - Mangled nmc file
start property read <0xffffcacc>

Seems like the FPGA Editor tool has problems with POWER and GND
connections
(see former post http://groups.google.com/groups?selm=72480649.0210271033.535836f4%40posting.google.com)

In my case, that gnd/pwr connections are inferred by the synthesis
tool, and it's not easy to get rid of them.

My question is if this problem is solved in the ISE 5.2 version? Does
it worth to upgrade the tool? Other ideas of overcome this problem?
Are there anyone having the same problem?

Thanks,

Santi

------------------------------------
Santiago Esteban Zorita
Electric and Electronic Engineering dept.
University of Strathclyde
santi@eee.strath.ac.uk
------------------------------------

 

[Chen Wei Tseng]

Hi Santi,

Since 5.x version, FPGA Editor no longer support hard macro containing Vcc comps. What you'll have to do is
declear pins that connects to Vcc as external macro pin and connect the pin to Vcc or '1' in your source
code.

Regards, Wei

Santi wrote:

Hi all!

I'm trying to make a hard macro of a design and I got that error:

FATAL_ERROR:Ncd:basncmacrodef.c:1466:1.19.2.1 - Mangled nmc file
start property read <0xffffcacc

Seems like the FPGA Editor tool has problems with POWER and GND
connections
(see former post http://groups.google.com/groups?selm=72480649.0210271033.535836f4%40posting.google.com)

In my case, that gnd/pwr connections are inferred by the synthesis
tool, and it's not easy to get rid of them.

My question is if this problem is solved in the ISE 5.2 version? Does
it worth to upgrade the tool? Other ideas of overcome this problem?
Are there anyone having the same problem?

Thanks,

Santi

------------------------------------
Santiago Esteban Zorita
Electric and Electronic Engineering dept.
University of Strathclyde
santi@eee.strath.ac.uk
------------------------------------

 

[Santi]

Chen Wei Tseng <chenwei.tseng@xilinx.com> wrote in message news:<3F0319FA.8D327A@xilinx.com>...

Hi Santi,

Since 5.x version, FPGA Editor no longer support hard macro containing Vcc comps. What you'll have to do is
declear pins that connects to Vcc as external macro pin and connect the pin to Vcc or '1' in your source
code.

Regards, Wei

Hi Wei,

The problem is the VCC/GND are inferred by the synthesis tool,
therefore I can't get rid of them unless there is a way of telling to
Synplify not to use them.

I find pretty ackward that the former versions of the ISE supported it
and not the newers.

Thanks,

Santi