FPGA config sizes

J

John Larkin

Guest
We're planning a new universal boot loader for a family of ST
processors. The uP would host the loader in a bit of local flash and
read an outboard serial flash to get the specific application code and
one or more FPGA configurations.

So, how many config bits might there be for a modern mid-range FPGA
doing a moderately complex application?

I think we could enable compression too.

Please consider this a PHB type question. I don't do FPGA development
myself, past whiteboarding.

--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com
 
Am 08.11.19 um 20:08 schrieb John Larkin:
We're planning a new universal boot loader for a family of ST
processors. The uP would host the loader in a bit of local flash and
read an outboard serial flash to get the specific application code and
one or more FPGA configurations.

So, how many config bits might there be for a modern mid-range FPGA
doing a moderately complex application?

I think we could enable compression too.

Please consider this a PHB type question. I don't do FPGA development
myself, past whiteboarding.
Click to expand...

The size of the programming file is in the data sheet. It is constant
and does not depend on the implemented circuitry.

Newer FPGAs may allow to program only some sectors of the chip.

regards, Gerhard
 
On Friday, November 8, 2019 at 2:09:04 PM UTC-5, John Larkin wrote:
We're planning a new universal boot loader for a family of ST
processors. The uP would host the loader in a bit of local flash and
read an outboard serial flash to get the specific application code and
one or more FPGA configurations.

So, how many config bits might there be for a modern mid-range FPGA
doing a moderately complex application?

I think we could enable compression too.

Please consider this a PHB type question. I don't do FPGA development
myself, past whiteboarding.
Click to expand...

Anyone know what a "PHB" type question is?

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209
 
On Friday, November 8, 2019 at 2:13:18 PM UTC-5, Gerhard Hoffmann wrote:
Am 08.11.19 um 20:08 schrieb John Larkin:


We're planning a new universal boot loader for a family of ST
processors. The uP would host the loader in a bit of local flash and
read an outboard serial flash to get the specific application code and
one or more FPGA configurations.

So, how many config bits might there be for a modern mid-range FPGA
doing a moderately complex application?

I think we could enable compression too.

Please consider this a PHB type question. I don't do FPGA development
myself, past whiteboarding.


The size of the programming file is in the data sheet. It is constant
and does not depend on the implemented circuitry.

Newer FPGAs may allow to program only some sectors of the chip.

regards, Gerhard
Click to expand...

I've never used compression on the bit stream, but I recall there is compression available, possibly even through the tools. I don't have any direct work experience with this, but I have a recollection that most of the bits in an FPGA bit stream are zeros. So some type of a RLL compression may be very useful.

Where have you seen info on programming only parts of chips? I recall some years back Xilinx talked about partial configuration, but they never got that working to the point it was generally available. I think they worked on it for a few large customers and they likely decided it wasn't worth the effort.

Now, instead of programming a part of an FPGA for different tasks, you can easily just use multiple FPGAs and program them individually. Lattice makes some very tiny FPGA packages. I mean cell phone tiny.

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209
 
On Friday, November 8, 2019 at 11:09:04 AM UTC-8, John Larkin wrote:
We're planning a new universal boot loader for a family of ST
processors. The uP would host the loader in a bit of local flash and
read an outboard serial flash to get the specific application code and
one or more FPGA configurations.

So, how many config bits might there be for a modern mid-range FPGA
doing a moderately complex application?
Click to expand...

Page 21:

https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf
 
fredag den 8. november 2019 kl. 21.20.55 UTC+1 skrev John Larkin:
On Fri, 8 Nov 2019 11:43:08 -0800 (PST), edward.ming.lee@gmail.com
wrote:

On Friday, November 8, 2019 at 11:09:04 AM UTC-8, John Larkin wrote:
We're planning a new universal boot loader for a family of ST
processors. The uP would host the loader in a bit of local flash and
read an outboard serial flash to get the specific application code and
one or more FPGA configurations.

So, how many config bits might there be for a modern mid-range FPGA
doing a moderately complex application?


Page 21:

https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf

I was just wondering what sort of config file sizes people were really
seeing. Maybe compressed, too.

Looks like a 1 or 2 Gbit serial flash is cheap nowadays. I can imagine
storing maybe four configs in the flash chip.
Click to expand...

http://stm32f4-discovery.net/2014/07/library-21-read-sd-card-fatfs-stm32f4xx-devices/
 
On 08/11/2019 19:08, John Larkin wrote:
We're planning a new universal boot loader for a family of ST
processors. The uP would host the loader in a bit of local flash and
read an outboard serial flash to get the specific application code and
one or more FPGA configurations.

So, how many config bits might there be for a modern mid-range FPGA
doing a moderately complex application?

I think we could enable compression too.

Please consider this a PHB type question. I don't do FPGA development
myself, past whiteboarding.
Click to expand...

The uncompressed FPGA configuration file size does not change with the
device utilization.
You need to look at the data sheet for the particular device.
Obviously the compressed file size will be variable - with anything from
0% to near 100% compression ratio dependent on content and compression
algorithm.
 
On Fri, 8 Nov 2019 11:43:08 -0800 (PST), edward.ming.lee@gmail.com
wrote:

On Friday, November 8, 2019 at 11:09:04 AM UTC-8, John Larkin wrote:
We're planning a new universal boot loader for a family of ST
processors. The uP would host the loader in a bit of local flash and
read an outboard serial flash to get the specific application code and
one or more FPGA configurations.

So, how many config bits might there be for a modern mid-range FPGA
doing a moderately complex application?


Page 21:

https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf
Click to expand...

I was just wondering what sort of config file sizes people were really
seeing. Maybe compressed, too.

Looks like a 1 or 2 Gbit serial flash is cheap nowadays. I can imagine
storing maybe four configs in the flash chip.



--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com
 
On Fri, 8 Nov 2019 12:32:39 -0800 (PST), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

fredag den 8. november 2019 kl. 21.20.55 UTC+1 skrev John Larkin:
On Fri, 8 Nov 2019 11:43:08 -0800 (PST), edward.ming.lee@gmail.com
wrote:

On Friday, November 8, 2019 at 11:09:04 AM UTC-8, John Larkin wrote:
We're planning a new universal boot loader for a family of ST
processors. The uP would host the loader in a bit of local flash and
read an outboard serial flash to get the specific application code and
one or more FPGA configurations.

So, how many config bits might there be for a modern mid-range FPGA
doing a moderately complex application?


Page 21:

https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf

I was just wondering what sort of config file sizes people were really
seeing. Maybe compressed, too.

Looks like a 1 or 2 Gbit serial flash is cheap nowadays. I can imagine
storing maybe four configs in the flash chip.


http://stm32f4-discovery.net/2014/07/library-21-read-sd-card-fatfs-stm32f4xx-devices/
Click to expand...

Interesting, but looks like overkill for a little resident boot
loader.

We have used SD cards with Zynq chips, but they already know how to
boot from SD.

https://www.dropbox.com/s/03r1b3zbrqa9lme/P5_SD_1.jpg?raw=1



--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com
 
fredag den 8. november 2019 kl. 20.29.31 UTC+1 skrev Rick C:
On Friday, November 8, 2019 at 2:13:18 PM UTC-5, Gerhard Hoffmann wrote:
Am 08.11.19 um 20:08 schrieb John Larkin:


We're planning a new universal boot loader for a family of ST
processors. The uP would host the loader in a bit of local flash and
read an outboard serial flash to get the specific application code and
one or more FPGA configurations.

So, how many config bits might there be for a modern mid-range FPGA
doing a moderately complex application?

I think we could enable compression too.

Please consider this a PHB type question. I don't do FPGA development
myself, past whiteboarding.


The size of the programming file is in the data sheet. It is constant
and does not depend on the implemented circuitry.

Newer FPGAs may allow to program only some sectors of the chip.

regards, Gerhard

I've never used compression on the bit stream, but I recall there is compression available, possibly even through the tools. I don't have any direct work experience with this, but I have a recollection that most of the bits in an FPGA bit stream are zeros. So some type of a RLL compression may be very useful.
Click to expand...

the bitstream can make the bit file much smaller depending on how much you use of the fpga, but if you decide to encrypt the bitstream and put a key in the
fpga you are back at the maximum size
 
On 2019-11-08 20:23, Rick C wrote:
On Friday, November 8, 2019 at 2:09:04 PM UTC-5, John Larkin wrote:
We're planning a new universal boot loader for a family of ST
processors. The uP would host the loader in a bit of local flash and
read an outboard serial flash to get the specific application code and
one or more FPGA configurations.

So, how many config bits might there be for a modern mid-range FPGA
doing a moderately complex application?

I think we could enable compression too.

Please consider this a PHB type question. I don't do FPGA development
myself, past whiteboarding.

Anyone know what a "PHB" type question is?
Click to expand...

Pointy-Haired Boss, a character from the Dilbert cartoon.
The theme of the cartoon is workplace relations.

Jeroen Belleman
 
On Friday, November 8, 2019 at 4:32:43 PM UTC-5, Jeroen Belleman wrote:
On 2019-11-08 20:23, Rick C wrote:

Anyone know what a "PHB" type question is?


Pointy-Haired Boss, a character from the Dilbert cartoon.
The theme of the cartoon is workplace relations.
Click to expand...

Sloman is the model for the 'Wally' character?
 
fredag den 8. november 2019 kl. 23.45.40 UTC+1 skrev Rick C:
On Friday, November 8, 2019 at 4:32:43 PM UTC-5, Jeroen Belleman wrote:
On 2019-11-08 20:23, Rick C wrote:
On Friday, November 8, 2019 at 2:09:04 PM UTC-5, John Larkin wrote:
We're planning a new universal boot loader for a family of ST
processors. The uP would host the loader in a bit of local flash and
read an outboard serial flash to get the specific application code and
one or more FPGA configurations.

So, how many config bits might there be for a modern mid-range FPGA
doing a moderately complex application?

I think we could enable compression too.

Please consider this a PHB type question. I don't do FPGA development
myself, past whiteboarding.

Anyone know what a "PHB" type question is?


Pointy-Haired Boss, a character from the Dilbert cartoon.
The theme of the cartoon is workplace relations.

No wonder a Google search didn't find anything. Just the reference is obscure enough, using an abbreviation makes it local jargon.
Click to expand...

I think we are well past the point where a reference to PHB can be considered obscure in engineering circles

https://en.wikipedia.org/wiki/Pointy-haired_Boss
 
On Friday, November 8, 2019 at 6:07:03 PM UTC-5, Lasse Langwadt Christensen wrote:
fredag den 8. november 2019 kl. 23.45.40 UTC+1 skrev Rick C:
On Friday, November 8, 2019 at 4:32:43 PM UTC-5, Jeroen Belleman wrote:
On 2019-11-08 20:23, Rick C wrote:
On Friday, November 8, 2019 at 2:09:04 PM UTC-5, John Larkin wrote:
We're planning a new universal boot loader for a family of ST
processors. The uP would host the loader in a bit of local flash and
read an outboard serial flash to get the specific application code and
one or more FPGA configurations.

So, how many config bits might there be for a modern mid-range FPGA
doing a moderately complex application?

I think we could enable compression too.

Please consider this a PHB type question. I don't do FPGA development
myself, past whiteboarding.

Anyone know what a "PHB" type question is?


Pointy-Haired Boss, a character from the Dilbert cartoon.
The theme of the cartoon is workplace relations.

No wonder a Google search didn't find anything. Just the reference is obscure enough, using an abbreviation makes it local jargon.


I think we are well past the point where a reference to PHB can be considered obscure in engineering circles

https://en.wikipedia.org/wiki/Pointy-haired_Boss
Click to expand...

https://lmgtfy.com/?q=phb&s=g

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209
 
On Friday, November 8, 2019 at 4:32:43 PM UTC-5, Jeroen Belleman wrote:
On 2019-11-08 20:23, Rick C wrote:
On Friday, November 8, 2019 at 2:09:04 PM UTC-5, John Larkin wrote:
We're planning a new universal boot loader for a family of ST
processors. The uP would host the loader in a bit of local flash and
read an outboard serial flash to get the specific application code and
one or more FPGA configurations.

So, how many config bits might there be for a modern mid-range FPGA
doing a moderately complex application?

I think we could enable compression too.

Please consider this a PHB type question. I don't do FPGA development
myself, past whiteboarding.

Anyone know what a "PHB" type question is?


Pointy-Haired Boss, a character from the Dilbert cartoon.
The theme of the cartoon is workplace relations.
Click to expand...

No wonder a Google search didn't find anything. Just the reference is obscure enough, using an abbreviation makes it local jargon.

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209
 
On Fri, 08 Nov 2019 12:20:44 -0800, John Larkin wrote:

On Fri, 8 Nov 2019 11:43:08 -0800 (PST), edward.ming.lee@gmail.com
wrote:

On Friday, November 8, 2019 at 11:09:04 AM UTC-8, John Larkin wrote:
We're planning a new universal boot loader for a family of ST
processors. The uP would host the loader in a bit of local flash and
read an outboard serial flash to get the specific application code and
one or more FPGA configurations.

So, how many config bits might there be for a modern mid-range FPGA
doing a moderately complex application?


Page 21:

https://www.xilinx.com/support/documentation/user_guides/ug570-
ultrascale-configuration.pdf

I was just wondering what sort of config file sizes people were really
seeing. Maybe compressed, too.

Looks like a 1 or 2 Gbit serial flash is cheap nowadays. I can imagine
storing maybe four configs in the flash chip.
Click to expand...

The built-in bitstream compression merely reuses indentical configuration
frames. This gives good results on an empty FPGA, but poor results on a
moderately utilised one.

We use gzip -9 here. From this thread on the Xilinx forum,
https://forums.xilinx.com/t5/FPGA-Configuration/Complete-reconfiguration-
with-GZip-ed-bitstream/m-p/667837#M4437
I can see that this gives a compression ranging from 28:1 to 2.8:1, but
usually about 3.8 : 1 for a typical FPGA.
Please note that ungzipping is only possible in software. You will not
be able to use that method if configuring an FPGA directly from a PROM.

Regards,
Allan
 
On 08/11/2019 19:08, John Larkin wrote:
We're planning a new universal boot loader for a family of ST
processors. The uP would host the loader in a bit of local flash and
read an outboard serial flash to get the specific application code and
one or more FPGA configurations.

So, how many config bits might there be for a modern mid-range FPGA
doing a moderately complex application?

I think we could enable compression too.

Please consider this a PHB type question. I don't do FPGA development
myself, past whiteboarding.

From Lattice ECP5 sysCONFIG Usage Guide FPGA-TN-02039.
Click to expand...

LFE5-45 - 8.86Mb


From Xilinx UG470
Xilinx Artix 35T and 50T need the same 17.536 Mb

MK
 
On 09/11/2019 09:49, Michael Kellett wrote:
On 08/11/2019 19:08, John Larkin wrote:


We're planning a new universal boot loader for a family of ST
processors. The uP would host the loader in a bit of local flash and
read an outboard serial flash to get the specific application code and
one or more FPGA configurations.

So, how many config bits might there be for a modern mid-range FPGA
doing a moderately complex application?

I think we could enable compression too.

Please consider this a PHB type question. I don't do FPGA development
myself, past whiteboarding.

From Lattice ECP5 sysCONFIG Usage Guide FPGA-TN-02039.

LFE5-45 - 8.86Mb


From Xilinx UG470
Xilinx Artix 35T and 50T need the same 17.536 Mb

MK
Why complicate things with memory soooo cheap ??? Just store raw data...
Click to expand...
 
On Sat, 09 Nov 2019 01:27:44 -0600, Allan Herriman
<allanherriman@hotmail.com> wrote:

On Fri, 08 Nov 2019 12:20:44 -0800, John Larkin wrote:

On Fri, 8 Nov 2019 11:43:08 -0800 (PST), edward.ming.lee@gmail.com
wrote:

On Friday, November 8, 2019 at 11:09:04 AM UTC-8, John Larkin wrote:
We're planning a new universal boot loader for a family of ST
processors. The uP would host the loader in a bit of local flash and
read an outboard serial flash to get the specific application code and
one or more FPGA configurations.

So, how many config bits might there be for a modern mid-range FPGA
doing a moderately complex application?


Page 21:

https://www.xilinx.com/support/documentation/user_guides/ug570-
ultrascale-configuration.pdf

I was just wondering what sort of config file sizes people were really
seeing. Maybe compressed, too.

Looks like a 1 or 2 Gbit serial flash is cheap nowadays. I can imagine
storing maybe four configs in the flash chip.


The built-in bitstream compression merely reuses indentical configuration
frames. This gives good results on an empty FPGA, but poor results on a
moderately utilised one.

We use gzip -9 here. From this thread on the Xilinx forum,
https://forums.xilinx.com/t5/FPGA-Configuration/Complete-reconfiguration-
with-GZip-ed-bitstream/m-p/667837#M4437
I can see that this gives a compression ranging from 28:1 to 2.8:1, but
usually about 3.8 : 1 for a typical FPGA.
Please note that ungzipping is only possible in software. You will not
be able to use that method if configuring an FPGA directly from a PROM.

Regards,
Allan
Click to expand...

I did a little compression thing, file compressor in PowerBasic and
unpacker in assembly, based on finding runs of 1s or 0s. Typical
compression was 2:1 or better, and the decoder was small and very
fast. It configured most FPGAs faster than the un-compressed version,
because the 1-or-0 unpack bursts were the tightest possible loops.

I wouldn't use that again, because an ARM with hardware SPI or QSPI
interfaces, from serial flash and to the FPGA config pins, would
probably be faster.



--

John Larkin Highland Technology, Inc

lunatic fringe electronics
 
On Sat, 9 Nov 2019 11:15:56 +0000, TTman <kraken.sankey@gmail.com>
wrote:

On 09/11/2019 09:49, Michael Kellett wrote:
On 08/11/2019 19:08, John Larkin wrote:


We're planning a new universal boot loader for a family of ST
processors. The uP would host the loader in a bit of local flash and
read an outboard serial flash to get the specific application code and
one or more FPGA configurations.

So, how many config bits might there be for a modern mid-range FPGA
doing a moderately complex application?

I think we could enable compression too.

Please consider this a PHB type question. I don't do FPGA development
myself, past whiteboarding.

From Lattice ECP5 sysCONFIG Usage Guide FPGA-TN-02039.

LFE5-45 - 8.86Mb


From Xilinx UG470
Xilinx Artix 35T and 50T need the same 17.536 Mb

MK
Why complicate things with memory soooo cheap ??? Just store raw data...
Click to expand...

Compression could save bootup time. The Artix7 that I'm using now is
only 17 mbits, but some of the Vertix chips are approaching a gigabit.
Luckily, I can't afford them.

https://www.digikey.com/product-detail/en/xilinx-inc/XCVU37P-3FSVH2892E/122-XCVU37P-3FSVH2892E-ND/10445719

Probably lots of config bits.





--

John Larkin Highland Technology, Inc

lunatic fringe electronics
 
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