FPGA/ASIC design comparaison

[Oleg]

Hi,
I'd like to aske an important, for me, question :
I have to compare the improvement of my design (the new version and
the old one) with the same design that was implemented using ASIC. I
am using Xilinx Virtex II for my implementations. The comparaison is
about the area efficiency ratio : area(new_design)/area(old_design)
and
speed(new_design)/speed(old_design) and this comparaison is made for
FPGA and ASIC implementations. The probleme is : do i have to take
in consideration the number of 4 input LUT's used as a route-thru. I
think that the correcte totale number of used LUT's will be :
totale number of used LUT's "-" number of LUT's used as a route thru.
Is that correcte or i have to take them in account too???

Thank for any help

 

[Mike Treseler]

benkhalh@hotmail.com (Oleg) wrote in message news:<5f8ab9cc.0407051150.5254d7a8@posting.google.com>...

I'd like to aske an important, for me, question :
I have to compare the improvement of my design (the new version and
the old one) with the same design that was implemented using ASIC.

Synthesize/place+route all four cases and
compare the utilization and timing reports.

-- Mike Treseler