FPGA Area

[Shakes]

Hi all,

I have question on measuring FPGA area. Measuring area cost of the FPGA implementation is tricky because there
are several different area types LUT, FF, BRAM, DSP. Is there way look
at a uniform cost model which combines all of then.

1. Some early version of ISE had equivalent gate count number for an
VHDL implementation. But it's not available anymore.
2. Slices seems to be the common unit of comparison. This is consists
of LUT and FF. But how about BRAM, DSP.
Can I say estimate the BRAM cost like this?
One 6input LUT(V6) = 64 x 1 bit RAM
1 Slice = 4 LUT = 256 x 1 bit RAM
1BRAM = 36kb => 144 slices

For DSP, I wrote simple code with 25x18 multiplier and then 48 bit
accumulator and set no dsp usage in synthesis to get the slice number
as 154 slices. (This was done using a Virtex 6.)

Is this a good estimate?
Are they are any alternative ways to measure an uniform cost of FPGA
implementation?

Thanks in advance.

 

[Gabor]

Shakes wrote:

Hi all,

I have question on measuring FPGA area. Measuring area cost of the FPGA implementation is tricky because there
are several different area types LUT, FF, BRAM, DSP. Is there way look
at a uniform cost model which combines all of then.

1. Some early version of ISE had equivalent gate count number for an
VHDL implementation. But it's not available anymore.
2. Slices seems to be the common unit of comparison. This is consists
of LUT and FF. But how about BRAM, DSP.
Can I say estimate the BRAM cost like this?
One 6input LUT(V6) = 64 x 1 bit RAM
1 Slice = 4 LUT = 256 x 1 bit RAM
1BRAM = 36kb => 144 slices

For DSP, I wrote simple code with 25x18 multiplier and then 48 bit
accumulator and set no dsp usage in synthesis to get the slice number
as 154 slices. (This was done using a Virtex 6.)

Is this a good estimate?
Are they are any alternative ways to measure an uniform cost of FPGA
implementation?

Thanks in advance.

Unless your design is intended to be implemented in an ASIC, it doesn't
make a lot of sense to look for a uniform metric like gate count. In
an FPGA, you get a limited number of each resource. At least for
Xilinx tools, you also get a report showing the percentage of each
resource used by your design. If you wanted to know how many of
your designs fit in a given FPGA, or how much of the FPGA is left
over for other stuff, then the percentage of each resource is
the best way to look at it. If you insist on applying a single
metric, then I would suggest considering each resource based on
the number available. For example if your device has 14K LUTs
and 140 block RAMs, then a block RAM would be worth 100 LUTs
because that's the ratio of LUTs to BRAM in that device. Still,
an end user of your design would need to know the individual
numbers in order to get a useful estimate of the FPGA required
based on used and remaining resources.

-- Gabor

 

[rickman]

On Mar 6, 8:43 am, Shakes <shakith.ferna...@gmail.com> wrote:

Hi all,

I have question on measuring FPGA area. Measuring area cost of the FPGA implementation is tricky because there
are several different area types LUT, FF, BRAM, DSP. Is there way look
at a uniform cost model which combines all of then.

1. Some early version of ISE had equivalent gate count number for an
VHDL implementation. But it's not available anymore.
2. Slices seems to be the common unit of comparison. This is consists
of LUT and FF. But how about BRAM, DSP.
Can I say estimate the BRAM cost like this?
One 6input LUT(V6) = 64 x 1 bit RAM
1 Slice = 4 LUT = 256 x 1 bit RAM
1BRAM = 36kb => 144 slices

For DSP, I wrote simple code with 25x18 multiplier and then 48 bit
accumulator and set no dsp usage in synthesis to get the slice number
as 154 slices. (This was done using a Virtex 6.)

Is this a good estimate?
Are they are any alternative ways to measure an uniform cost of FPGA
implementation?

Thanks in advance.

I'm not clear on what you are trying to achieve. The point of
including RAM and DSP on FPGAs is to reduce the area used as well as
accelerate the speed of designs. So why would you want to count the
slice usage of a design that you expect will be implemented using DSP
blocks? Are you going to count the equivalent slices for a memory
based design?

What do you want this number for?

Rick

 

[glen herrmannsfeldt]

Shakes <shakith.fernando@gmail.com> wrote:

I have question on measuring FPGA area. Measuring area cost
of the FPGA implementation is tricky because there
are several different area types LUT, FF, BRAM, DSP. Is there way look
at a uniform cost model which combines all of then.

Useful measurments before BRAM and DSP were never very good,
but now it is close to impossible.

Why do you want such a measurment? The result might depend on why.

1. Some early version of ISE had equivalent gate count number for an
VHDL implementation. But it's not available anymore.
2. Slices seems to be the common unit of comparison. This is consists
of LUT and FF. But how about BRAM, DSP.

But slices usually have more than one LUT and FF, and many
are now using 6LUT instead of the previous 4LUT.

Can I say estimate the BRAM cost like this?

Many designs don't use BRAM at all, others might not use FF,
yet they are still on the chip.

One 6input LUT(V6) = 64 x 1 bit RAM
1 Slice = 4 LUT = 256 x 1 bit RAM
1BRAM = 36kb => 144 slices

The traditional ASIC method was the equivalent in 2 input NAND,
which is four transistors in CMOS. So the conversion was to
take the number of transistors and divide by four. Not so bad.

If you figure the average gates used in a LUT, convert with that.
An FF might be about four gate equivalent.

The usual SRAM cell is four transistors, plus one or two for gating,
plus address decoding. So 1.5 to 2 gates/bit might be close.

For DSP, I wrote simple code with 25x18 multiplier and then 48 bit
accumulator and set no dsp usage in synthesis to get the slice number
as 154 slices. (This was done using a Virtex 6.)

Is this a good estimate?
Are they are any alternative ways to measure an uniform
cost of FPGA implementation?

Not really. I have a design that is scalable, so I can vary the
amount of logic in a chip. For a fairly wide range, the speed is
almost inversely proportional to the amount of logic. That is
likely true for other designs. That means that if you give a size,
you also should give an appropriate speed.

-- glen

 

[Kolja Sulimma]

On Mar 6, 2:43 pm, Shakes <shakith.ferna...@gmail.com> wrote:

2. Slices seems to be the common unit of comparison.

Slices are often used, but they are a stupid way to compare area.
The real comparison for logic area is LUTs.
The number of slices will depend greatly on placement. In an FPGA
that is mostly empty a circuit might spread out evenly and it might be
that there is only one LUT placed into each slice.
The same circuit mapped to the same number of LUTs might take up
only half the number of slices if placed into a smaller FPGAs, because
each slice gets two LUTs. The LUTs in a slice are greatly
independent,
so this is almost always possible, the tools just don't do it if it
isn't
necessary.

The LUT count will remain the same in both cases, so that should be
used
for comparison.

Kolja

 

[Kolja Sulimma]

On Mar 6, 2:43 pm, Shakes <shakith.ferna...@gmail.com> wrote:

Is there a way to look at a uniform cost model which combines all of then?

No.
- A BRAM can be used ot implement a 7x7 multiplyer, but a multiplier
can't be used to implement a RAM.
- A BRAM can replace 1024 4-LUTs that are used as RAM or ROM, if they
are part of one address range. If the addresses are independent it can
only replace 1 LUT in the RAM case or 3 LUTs in the ROM case.
- A 18x18 multiplier can replace 18 LUTs used as adders or 54 LUTs
used as barrel shifters, but it will take 324 LUTs to replace the
multiplier

So, depending on application the conversion factors differ by three
orders of magnitude and conversion is not possible at all in some
cases.
You really have to treat these as seperate ressources.

There is some simplification possible:
The ration of LUTs to DFFs is very much in favor of the DFFs in most
FPGA architectures to simplify placement. It is very uncommon to run
out of DFFs in an FPGA that has enough LUTs for your design (if you
are not called Ray Andraka) so you could simply ignore DFF count in
the comparison.
Also: Multiplers tend to be either the limiting factor or not used at
all.

Kolja

 

[RCIngham]

Is there ... a uniform cost model which combines all of them?

No, and only a Pointy-Haired Boss would think that as simplistic a metri
as that was a useful measure.

As other posters have suggested, for a given target FPGA, the percentag
utilisation figures are useful, and if pushed by management for a singl
figure I would give the worst o
FFs/LUTs/BRAMs/DSPs/whatever-else-is-relevant.

If this is for an academic thesis, then it doesn't matter much what yo
put, because no-one in industry will read it...


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