J
john
Guest
Hello,
I interfaced two FPGAs with the Dual port RAM (SRAM). Dual port RAM
has 19 bit of address bus and 18 bit of data bus.I am using 14 bit of
data bus.
FPGA on the left hand side of the Dual port RAM is writing data to the
RAM, filling the DPR fully. So data is always there..
I am trying to implement the following scheme with the above mentioned
hardware.
Right hand side FPGA will generate the 19 bit address for the memory
and get the 14 bit data and concatenate that 14 bit data with the five
bit counter
number to generate another set of 19 bit address and retrived another
14 bit of data and send it to its destination.
So there is two kind of data in the memory, the one data is the Look
up table values and the other set of data is the refernce to the LUT
values.
I am implementing above scheme ( for Right hand side FPGA) with three
counters, one is 14 bit counter , two five bit counters, one five bit
multiplexer and
one fourteen bit multiplexer.
Now, the fourteen bit counter and the 14 bit data bus( out of 18 bit
data bus) are multiplexed through the 14 bit multiplexer. The two
five bit counters
are multiplexed through five bit multiplexer.
First the 14 bit mux. is selected for the 14 bit counter so the 14 MSB
bit address bits gets valid on the address bus, at the same time the
five bit mux.
will be selected for the five bit counter which will be used as the 5
LSB bits for the Adrress bus to compelete 19 bit address. After
getting the 14 bit
data out from the formed address, the 14bit mux. will be selected for
the 14 bit data bus and the retrived data from the previous address
will appear on the
14 bit MSB address bus lines and at the same time the 5bit mux. will
be selected for the other 5-bit counter inorder to complete the 19-bit
address inorder
to get the final 14 bit data. The 5 bit counter number will appear at
the LSB five bits of the address lines. These two numbers will be
concatenated too.
Off course, the first retrieved data is providing the base address for
the LUT table values and I am not adding any number to the base
address instead I am
concatenating the five bit number to it.
And I can do it because those numbers are 32 and 64 which are six and
seven bit number and they will always appear as the 14 bit MSB bits so
the five LSB
bits are always avaiable for concatenation.
sO, we have pointers in one section of the memroy and have data in
other section of the memory. So the FPGA gets its direction from the
pointer data that
which data value it needs to send out.
I am also attaching my code with the message. My questions are as
follows
1. I am not seeing the right number at the ouput? for example if the
number in the memory is 32 (00000000100000) then at
the output, I am seeing (00001100110011) or sometimes other different
number ?
2. Do I need a latch to store the data into the FPGA before its gets
to address bus?
3. If I need a latch then how it will be implemented?
4. The way I am reading the SRAM, Is it the right way?
Thanks
Regards
john
----Main Sequential Machine ( main program)--------
Library IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
------------------------------------------------------
Entity Read is
port (
Data_Bus : inout unsigned (13 downto 0);
Address_bus : inout unsigned (18 downto 0 );
Read_write: out std_logic;
Output_Enable : out std_logic;
DPR_CLK : in std_logic;
CE0: out std_logic;
CE1 : out std_logic;
LBL : out std_logic;
UBL : out std_logic;
input_signal : in std_logic;
ZZL: out std_logic:='0'; -- To keep the DPR awake!!!
SEML: out std_logic:='1';
OPTL : OUT std_logic;
output_signal : out std_logic;
Latch : out std_logic;
Data_out_bus : out unsigned (18 downto 0);
Request: out std_logic;
CPLD_READY : in std_logic;
OE1: in std_logic
);
End Read;
Architecture DPR_ARCH of Read IS
----------14-bit Counter-----------
Component counter
Port (
Qout : out unsigned (13 downto 0);
CLK : in std_logic;
P : in std_logic;
count_equal: out std_logic;
Reset_c: in std_logic
);
End Component;
---------Counter B (5-bit Channel counter)--------
Component counter_b
Port (
Qout_b : out unsigned (4 downto 0 ); -- 19 bit address bus output
CLK_b : in std_logic; -- Clock for the counter
Load_b : out std_logic; -- Load the intial count
CLRN_b : in std_logic; -- Reset the counter in the beginning
P_b : in std_logic; -- Increment the count
count_equal_b: out std_logic;
Reset_b: in std_logic
);
End Component;
--------Counter C ( 5- bit Sample counter)------
Component counter_c
Port (
Qout_c : out unsigned (9 downto 5 ); -- 19 bit address bus output
CLK_c : in std_logic; -- Clock for the counter
CLRN_c : in std_logic; -- Reset the counter in the beginning
P_c : in std_logic; -- Increment the count
count_equal_c: out std_logic;
Reset: in std_logic
);
End Component;
---------------5-bit Multiplexer---------
Component MUX
Port (
counter_b_datain: in unsigned( 4 downto 0);
counter_c_datain: in unsigned( 4 downto 0);
Select_line: in std_logic;
Data_output : inout unsigned ( 4 downto 0)
);
End Component;
---------------14 bit Multiplexer---------------
Component multiplexer is
Port (
Sel_line : in std_logic;
data_in_counter : in unsigned ( 13 downto 0);
data_in_data_bus : in unsigned ( 13 downto 0);
data_out_mux : out unsigned ( 13 downto 0)
);
End Component;
----------------------Signals for counter A----------------
Signal counter_A_data : unsigned (13 downto 0);
----------------------Signals for counter B----------------
Signal clearB :std_logic;
Signal incrementB : std_logic;
Signal equalsignalB : std_logic;
Signal LoadB: std_logic;
Signal DataoutB : unsigned ( 4 downto 0);
Signal DatainB: unsigned ( 4 downto 0);
Signal Reset_counter_b: std_logic;
----------------------Signals for counter C----------------
Signal clearc :std_logic;
Signal incrementc : std_logic;
Signal equalsignalc : std_logic;
Signal Loadc: std_logic;
Signal Dataoutc : unsigned ( 4 downto 0);
Signal Datainc: unsigned ( 4 downto 0);
Signal Reset_counter_C : std_logic;
Signal incrementc_2 : std_logic;
---------------Signals for the Multiplexer----------------
Signal countb_mux_datain : unsigned (4 downto 0);
Signal countc_mux_datain : unsigned ( 4 downto 0);
Signal mux_select : std_logic;
Signal mux_data_out : unsigned ( 4 downto 0);
Signal sel_output : std_logic;
----------------State "E" Decalarations-------------------
signal State : unsigned(2 downto 0);
signal nextstate : unsigned(2 downto 0);
constant E0 : unsigned(2 downto 0) := "000";
constant E1 : unsigned(2 downto 0) := "001";
constant E2 : unsigned(2 downto 0) := "010";
constant E3 : unsigned(2 downto 0) := "011";
constant E4 : unsigned(2 downto 0) := "100";
constant E5 : unsigned(2 downto 0) := "101";
constant E6 : unsigned(2 downto 0) := "110";
Signal SM_DIR : std_logic;
----------------State "G" decalarations------------------
Signal State_G : unsigned(7 downto 0);
signal nextstate_G : unsigned(7 downto 0);
constant G0 : unsigned(7 downto 0) := "00000000";
Signal SM_DIR_G :std_logic:='1';
---------------State "F" decalarations---------------------
Signal State_F : unsigned(1 downto 0);
signal nextstate_F : unsigned(1 downto 0);
constant F0 : unsigned(1 downto 0) := "00";
constant F1 : unsigned(1 downto 0) := "01";
Signal SM_DIR_F : std_logic:='1';
--Signals for 19-bit counter
Signal equalsignalA : std_logic;
Signal clear :std_logic;
Signal inc: std_logic;
Signal eq_signal : std_logic:='0';
Signal Load_A: std_logic;
Signal Load_B : std_logic;
Signal Reset_A : std_logic:='1';
Signal counter_clock : std_logic;
Signal Data_in : unsigned ( 13 downto 0);
-----------Signals for the 14- bit multiplexer------------
Signal sel_14bit_mux : std_logic;
--------------------Clock signals for the counter-B and counter-C-----
Signal counterb_clock : std_logic;
Signal counterc_clock : std_logic:='1';
--------------------------------------------------------------------------------
Begin
Latch<= not CPLD_READY ;
Data_out_bus(18 downto 14)<=countb_mux_datain;
---------------------------------------------------------------------------------
C0: counter port map (counter_A_data, DPR_CLK,inc,eq_signal,Reset_A);
CB: counter_b port map (countb_mux_datain, DPR_CLK, LoadB, clearB,
incrementB, equalsignalB, Reset_counter_b);
CC: counter_c port map
(countc_mux_datain,equalsignalB,Loadc,incrementc,equalsignalc,
Reset_counter_C);
M: MUX port map (countb_mux_datain,countc_mux_datain, LoadB
,Address_bus(4 downto 0));
M14: multiplexer port map (sel_14bit_mux,counter_A_data,Data_Bus,
Address_bus(18 downto 5));
CF: P2S_COUNTER port map (P2S_CLK,P2S_INC,P2S_compare,P2S_Reset);
-----------------------------------------------------------------------------------
Process (State,nextstate,SM_DIR)
Begin
Case State is
When E1=>
Reset_A<='0';
output_signal <='0';
Reset_counter_b<='0';
Reset_counter_C<='0';
sel_14bit_mux <='1';
mux_select <='0';
incrementB<='1';
LBL <='1';
UBL <='1';
CE0 <='1';
CE1 <='0';
Read_write <='1';
Output_Enable<='0';
Data_Bus<="ZZZZZZZZZZZZZZ";
If (SM_DIR='1') Then
nextstate<=E2;
End If;
-------------------------------------
When E2=>
-- Address ( Frame counter ) gets valid!
-- DPR will drive the Data Bus and data will get valid
-- on the data bus!
Reset_A<='0';
output_signal <='0';
Reset_counter_b<='0';
Reset_counter_C<='0';
sel_14bit_mux <='1';
mux_select <='0';
incrementB<='0';
UBL <='0';
LBL <='0';
CE0 <='0';
CE1 <='1';
Read_write <='1';
Output_Enable<='0';
If (SM_DIR = '1') then
nextstate<=E3;
End If;
--------------------------------------------
When E3 =>
-- Data got valid and routed to the address bus via multiplexer!
Reset_A<='0';
output_signal <='0';
Reset_counter_b<='0';
Reset_counter_C<='0';
sel_14bit_mux <='0'; --Data gets valid on Address bus
mux_select <='0';
incrementB<='0';
UBL <='0';
LBL <='0';
CE0 <='0';
CE1 <='1';
Output_Enable<='0';
Read_write <='1';
If (SM_DIR = '1') then
nextstate<=E4;
End if;
When E4=>
--Retrived Data from last state is getting valid in this state!!
Reset_A<='0';
sel_14bit_mux <='0';
Reset_counter_b<='0';
Reset_counter_C<='0';
mux_select <='1';
incrementB<='0';
output_signal <='0';
UBL <='1';
LBL <='1';
CE0 <='1';
CE1 <='0';
Output_Enable<='0';
Read_write <='1';
Data_Bus<="ZZZZZZZZZZZZZZ";
If (SM_DIR = '1') then
nextstate<=E5;
End if;
When E5=>
-- Final set of data is retrived.........
mux_select <='1';
Reset_A<='0';
Reset_counter_b<='0';
Reset_counter_C<='0';
sel_14bit_mux <='0';
incrementB<='0';
output_signal <='0';
UBL <='0';
LBL <='0';
CE0 <='0';
CE1 <='1';
Output_Enable<='0';
Read_write <='1';
--Data_out_bus(13 downto 0) <= Address_bus(13 downto 0);
--Data_out_bus(18 downto 14)<=Address_bus(18 downto 14);
If (SM_DIR = '1') then
nextstate<=E6;
End if;
When E6=>
-- Waitng for the CPLD_Ready signal to out put 19 bits!!!
If (CPLD_READY ='1') Then
mux_select <='1';
Reset_A<='0';
Reset_counter_b<='0';
Reset_counter_C<='0';
sel_14bit_mux <='0';
incrementB<='0';
output_signal <='0';
UBL <='0';
LBL <='0';
CE0 <='0';
CE1 <='1';
Output_Enable<='0';
Read_write <='1';
--Data_out_bus(13 downto 0) <= "01010101010101";
--Data_out_bus(18 downto 14) <= "10101";
Data_out_bus(13 downto 0) <= Address_bus(13 downto 0);
If (SM_DIR = '1') then
nextstate<=E1;
End If;
Else
mux_select <='1';
Reset_A<='0';
Reset_counter_b<='0';
Reset_counter_C<='0';
sel_14bit_mux <='0';
incrementB<='0';
output_signal <='0';
UBL <='0';
LBL <='0';
CE0 <='0';
CE1 <='1';
Output_Enable<='0';
Read_write <='1';
If (SM_DIR = '1') then
nextstate<=E6;
End If;
End If;
When others =>
nextstate <= E1;
End Case;
End Process;
----------------------------------------
Process (DPR_CLK)
Begin
If (DPR_CLK'event And DPR_CLK='1') Then
State <= nextstate;
SM_DIR <= OE1;
End If;
End Process;
--------------Counter'C' Process----------------
PROCESS(equalsignalB)
Begin
If ( equalsignalB'event AND equalsignalB='0') then
State_G <= nextstate_G;
SM_DIR_G <= '1';
End If;
End Process;
---------Working area for the Counter C ( Sample Counter )----
PROCESS(State_G,nextstate_G,SM_DIR_G)
Begin
Case State_G is
When G0=>
If (SM_DIR_G='1') Then
incrementc <= '1';
nextstate_G <= G0;
End If;
When others =>
nextstate_G <= G0;
End Case;
End Process;
-----------Counter 'A' 14 bit counter process---
Process(equalsignalc)
Begin
If (equalsignalc'event AND equalsignalc='0') then
State_F <= nextstate_F;
SM_DIR_F <= '1';
End If;
End Process;
------------Working area for the counterA-----
PROCESS(State_F,nextstate_F,SM_DIR_F)
Begin
Case State_F is
When F0=>
If (SM_DIR_F='1') Then
inc <= '1';
nextstate_F <= F0;
End If;
When others =>
nextstate_F <= F0;
End Case;
End process;
------------------------------------------
End DPR_ARCH;
---------------------14 -bit counter (Frame
counter)-------------------
Library IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
Entity counter is
Port (
-- temp : out unsigned ( 3 downto 0);
Qout : out unsigned (13 downto 0);--:="11111111111111"; -- 19 bit
address bus output
--Din
ut unsigned (13 downto 0); -- 19 bit address bus input
CLK : in std_logic; -- Clock for the counter
P : in std_logic; -- Increment the count
count_equal: out std_logic;
Reset_c: in std_logic
);
End counter;
Architecture count_arch of counter is
Signal Q : unsigned (13 downto 0);
Signal D : unsigned (13 downto 0):="00000000000000";
Begin
--count_equal<=Q(1);
Process(Clk, Reset_c)
Begin
If (Reset_c = '1') then
-- count_equal <='0';
Q(13 downto 0) <= ('0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', '0' );
Qout<=Q;
Elsif (Clk='1' and Clk'event) then
If (P = '0') then
Q <= Q + 1;
Qout<=Q;
--count_equal <='0';
If(Q=D) Then
-- count_equal<='1';
Q(13 downto 0) <= ( '0', '0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0');
Qout<=Q;
End If;
End If;
--End If;
End if;
End process;
End count_arch ;
------------------14 bit Multiplexer----------------
Library IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
Entity multiplexer is
Port (
--its_clk : in std_logic;
Sel_line : in std_logic;
data_in_counter : in unsigned ( 13 downto 0);
data_in_data_bus : in unsigned ( 13 downto 0);
data_out_mux : out unsigned ( 13 downto 0)
);
End multiplexer;
Architecture muxq of multiplexer is
Begi
Process (Sel_line)
Begin
Case Sel_line is
When '1'=>
data_out_mux <= data_in_counter;
When '0'=>
data_out_mux <=data_in_data_bus;
When others =>
data_out_mux <="ZZZZZZZZZZZZZZ";
End case;
End process;
End muxq;
-----------5 bit counter------------------
Library IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
Entity counter_b is
Port (
Qout_b : out unsigned (4 downto 0 ); -- 19 bit address bus output
--Din_b : in unsigned (4 downto 0); -- 19 bit address bus input
CLK_b : in std_logic; -- Clock for the counter
Load_b : out std_logic; -- Load the intial count
CLRN_b : in std_logic; -- Reset the counter in the beginning
P_b : in std_logic; -- Increment the count
count_equal_b: out std_logic;
Reset_b: in std_logic
);
End counter_b;
Architecture count_arch_b of counter_b is
Signal get_equal_b: std_logic;
Signal Q_b : unsigned (4 downto 0);
Signal D_b : unsigned ( 4 downto 0):="00011";
Begin
count_equal_b<=Q_b(4);
--Load_b <= Q_b(4);
Process(CLK_b,Reset_b)
Begin
If ( Reset_b='1') Then
Q_b <= ('0', '0', '0', '0', '0');
Qout_b <= Q_b;
Load_b<='0';
Else If (CLK_b='1' and CLK_b'event) then
If (P_b='1') Then
Q_b<=Q_b +1;
Qout_b<= Q_b;
Load_b<='0';
If (Q_b= D_b) Then
Load_b<='1';
Q_b <= ('0', '0', '0', '0', '0');
Qout_b<= Q_b;
End If;
End If;
End if;
End If;
End process;
End count_arch_b ;
-------------5 bit multiplexer--------------
Library IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
Entity MUX is
Port (
counter_b_datain: in unsigned( 9 downto 5);
counter_c_datain: in unsigned( 9 downto 5);
Select_line: in std_logic;
Data_output : out unsigned ( 9 downto 5)
);
End MUX;
Architecture behav of MUX is
Begin
Process(Select_line)
Begin
Case Select_line is
When '1'=>
Data_output <= counter_c_datain;
When '0'=>
Data_output <= counter_b_datain;
When others=>
Data_output <= "00000";
End Case;
End process;
End behav;
-----X--------------X-------------------X---------------------------X-----------------
I interfaced two FPGAs with the Dual port RAM (SRAM). Dual port RAM
has 19 bit of address bus and 18 bit of data bus.I am using 14 bit of
data bus.
FPGA on the left hand side of the Dual port RAM is writing data to the
RAM, filling the DPR fully. So data is always there..
I am trying to implement the following scheme with the above mentioned
hardware.
Right hand side FPGA will generate the 19 bit address for the memory
and get the 14 bit data and concatenate that 14 bit data with the five
bit counter
number to generate another set of 19 bit address and retrived another
14 bit of data and send it to its destination.
So there is two kind of data in the memory, the one data is the Look
up table values and the other set of data is the refernce to the LUT
values.
I am implementing above scheme ( for Right hand side FPGA) with three
counters, one is 14 bit counter , two five bit counters, one five bit
multiplexer and
one fourteen bit multiplexer.
Now, the fourteen bit counter and the 14 bit data bus( out of 18 bit
data bus) are multiplexed through the 14 bit multiplexer. The two
five bit counters
are multiplexed through five bit multiplexer.
First the 14 bit mux. is selected for the 14 bit counter so the 14 MSB
bit address bits gets valid on the address bus, at the same time the
five bit mux.
will be selected for the five bit counter which will be used as the 5
LSB bits for the Adrress bus to compelete 19 bit address. After
getting the 14 bit
data out from the formed address, the 14bit mux. will be selected for
the 14 bit data bus and the retrived data from the previous address
will appear on the
14 bit MSB address bus lines and at the same time the 5bit mux. will
be selected for the other 5-bit counter inorder to complete the 19-bit
address inorder
to get the final 14 bit data. The 5 bit counter number will appear at
the LSB five bits of the address lines. These two numbers will be
concatenated too.
Off course, the first retrieved data is providing the base address for
the LUT table values and I am not adding any number to the base
address instead I am
concatenating the five bit number to it.
And I can do it because those numbers are 32 and 64 which are six and
seven bit number and they will always appear as the 14 bit MSB bits so
the five LSB
bits are always avaiable for concatenation.
sO, we have pointers in one section of the memroy and have data in
other section of the memory. So the FPGA gets its direction from the
pointer data that
which data value it needs to send out.
I am also attaching my code with the message. My questions are as
follows
1. I am not seeing the right number at the ouput? for example if the
number in the memory is 32 (00000000100000) then at
the output, I am seeing (00001100110011) or sometimes other different
number ?
2. Do I need a latch to store the data into the FPGA before its gets
to address bus?
3. If I need a latch then how it will be implemented?
4. The way I am reading the SRAM, Is it the right way?
Thanks
Regards
john
----Main Sequential Machine ( main program)--------
Library IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
------------------------------------------------------
Entity Read is
port (
Data_Bus : inout unsigned (13 downto 0);
Address_bus : inout unsigned (18 downto 0 );
Read_write: out std_logic;
Output_Enable : out std_logic;
DPR_CLK : in std_logic;
CE0: out std_logic;
CE1 : out std_logic;
LBL : out std_logic;
UBL : out std_logic;
input_signal : in std_logic;
ZZL: out std_logic:='0'; -- To keep the DPR awake!!!
SEML: out std_logic:='1';
OPTL : OUT std_logic;
output_signal : out std_logic;
Latch : out std_logic;
Data_out_bus : out unsigned (18 downto 0);
Request: out std_logic;
CPLD_READY : in std_logic;
OE1: in std_logic
);
End Read;
Architecture DPR_ARCH of Read IS
----------14-bit Counter-----------
Component counter
Port (
Qout : out unsigned (13 downto 0);
CLK : in std_logic;
P : in std_logic;
count_equal: out std_logic;
Reset_c: in std_logic
);
End Component;
---------Counter B (5-bit Channel counter)--------
Component counter_b
Port (
Qout_b : out unsigned (4 downto 0 ); -- 19 bit address bus output
CLK_b : in std_logic; -- Clock for the counter
Load_b : out std_logic; -- Load the intial count
CLRN_b : in std_logic; -- Reset the counter in the beginning
P_b : in std_logic; -- Increment the count
count_equal_b: out std_logic;
Reset_b: in std_logic
);
End Component;
--------Counter C ( 5- bit Sample counter)------
Component counter_c
Port (
Qout_c : out unsigned (9 downto 5 ); -- 19 bit address bus output
CLK_c : in std_logic; -- Clock for the counter
CLRN_c : in std_logic; -- Reset the counter in the beginning
P_c : in std_logic; -- Increment the count
count_equal_c: out std_logic;
Reset: in std_logic
);
End Component;
---------------5-bit Multiplexer---------
Component MUX
Port (
counter_b_datain: in unsigned( 4 downto 0);
counter_c_datain: in unsigned( 4 downto 0);
Select_line: in std_logic;
Data_output : inout unsigned ( 4 downto 0)
);
End Component;
---------------14 bit Multiplexer---------------
Component multiplexer is
Port (
Sel_line : in std_logic;
data_in_counter : in unsigned ( 13 downto 0);
data_in_data_bus : in unsigned ( 13 downto 0);
data_out_mux : out unsigned ( 13 downto 0)
);
End Component;
----------------------Signals for counter A----------------
Signal counter_A_data : unsigned (13 downto 0);
----------------------Signals for counter B----------------
Signal clearB :std_logic;
Signal incrementB : std_logic;
Signal equalsignalB : std_logic;
Signal LoadB: std_logic;
Signal DataoutB : unsigned ( 4 downto 0);
Signal DatainB: unsigned ( 4 downto 0);
Signal Reset_counter_b: std_logic;
----------------------Signals for counter C----------------
Signal clearc :std_logic;
Signal incrementc : std_logic;
Signal equalsignalc : std_logic;
Signal Loadc: std_logic;
Signal Dataoutc : unsigned ( 4 downto 0);
Signal Datainc: unsigned ( 4 downto 0);
Signal Reset_counter_C : std_logic;
Signal incrementc_2 : std_logic;
---------------Signals for the Multiplexer----------------
Signal countb_mux_datain : unsigned (4 downto 0);
Signal countc_mux_datain : unsigned ( 4 downto 0);
Signal mux_select : std_logic;
Signal mux_data_out : unsigned ( 4 downto 0);
Signal sel_output : std_logic;
----------------State "E" Decalarations-------------------
signal State : unsigned(2 downto 0);
signal nextstate : unsigned(2 downto 0);
constant E0 : unsigned(2 downto 0) := "000";
constant E1 : unsigned(2 downto 0) := "001";
constant E2 : unsigned(2 downto 0) := "010";
constant E3 : unsigned(2 downto 0) := "011";
constant E4 : unsigned(2 downto 0) := "100";
constant E5 : unsigned(2 downto 0) := "101";
constant E6 : unsigned(2 downto 0) := "110";
Signal SM_DIR : std_logic;
----------------State "G" decalarations------------------
Signal State_G : unsigned(7 downto 0);
signal nextstate_G : unsigned(7 downto 0);
constant G0 : unsigned(7 downto 0) := "00000000";
Signal SM_DIR_G :std_logic:='1';
---------------State "F" decalarations---------------------
Signal State_F : unsigned(1 downto 0);
signal nextstate_F : unsigned(1 downto 0);
constant F0 : unsigned(1 downto 0) := "00";
constant F1 : unsigned(1 downto 0) := "01";
Signal SM_DIR_F : std_logic:='1';
--Signals for 19-bit counter
Signal equalsignalA : std_logic;
Signal clear :std_logic;
Signal inc: std_logic;
Signal eq_signal : std_logic:='0';
Signal Load_A: std_logic;
Signal Load_B : std_logic;
Signal Reset_A : std_logic:='1';
Signal counter_clock : std_logic;
Signal Data_in : unsigned ( 13 downto 0);
-----------Signals for the 14- bit multiplexer------------
Signal sel_14bit_mux : std_logic;
--------------------Clock signals for the counter-B and counter-C-----
Signal counterb_clock : std_logic;
Signal counterc_clock : std_logic:='1';
--------------------------------------------------------------------------------
Begin
Latch<= not CPLD_READY ;
Data_out_bus(18 downto 14)<=countb_mux_datain;
---------------------------------------------------------------------------------
C0: counter port map (counter_A_data, DPR_CLK,inc,eq_signal,Reset_A);
CB: counter_b port map (countb_mux_datain, DPR_CLK, LoadB, clearB,
incrementB, equalsignalB, Reset_counter_b);
CC: counter_c port map
(countc_mux_datain,equalsignalB,Loadc,incrementc,equalsignalc,
Reset_counter_C);
M: MUX port map (countb_mux_datain,countc_mux_datain, LoadB
,Address_bus(4 downto 0));
M14: multiplexer port map (sel_14bit_mux,counter_A_data,Data_Bus,
Address_bus(18 downto 5));
CF: P2S_COUNTER port map (P2S_CLK,P2S_INC,P2S_compare,P2S_Reset);
-----------------------------------------------------------------------------------
Process (State,nextstate,SM_DIR)
Begin
Case State is
When E1=>
Reset_A<='0';
output_signal <='0';
Reset_counter_b<='0';
Reset_counter_C<='0';
sel_14bit_mux <='1';
mux_select <='0';
incrementB<='1';
LBL <='1';
UBL <='1';
CE0 <='1';
CE1 <='0';
Read_write <='1';
Output_Enable<='0';
Data_Bus<="ZZZZZZZZZZZZZZ";
If (SM_DIR='1') Then
nextstate<=E2;
End If;
-------------------------------------
When E2=>
-- Address ( Frame counter ) gets valid!
-- DPR will drive the Data Bus and data will get valid
-- on the data bus!
Reset_A<='0';
output_signal <='0';
Reset_counter_b<='0';
Reset_counter_C<='0';
sel_14bit_mux <='1';
mux_select <='0';
incrementB<='0';
UBL <='0';
LBL <='0';
CE0 <='0';
CE1 <='1';
Read_write <='1';
Output_Enable<='0';
If (SM_DIR = '1') then
nextstate<=E3;
End If;
--------------------------------------------
When E3 =>
-- Data got valid and routed to the address bus via multiplexer!
Reset_A<='0';
output_signal <='0';
Reset_counter_b<='0';
Reset_counter_C<='0';
sel_14bit_mux <='0'; --Data gets valid on Address bus
mux_select <='0';
incrementB<='0';
UBL <='0';
LBL <='0';
CE0 <='0';
CE1 <='1';
Output_Enable<='0';
Read_write <='1';
If (SM_DIR = '1') then
nextstate<=E4;
End if;
When E4=>
--Retrived Data from last state is getting valid in this state!!
Reset_A<='0';
sel_14bit_mux <='0';
Reset_counter_b<='0';
Reset_counter_C<='0';
mux_select <='1';
incrementB<='0';
output_signal <='0';
UBL <='1';
LBL <='1';
CE0 <='1';
CE1 <='0';
Output_Enable<='0';
Read_write <='1';
Data_Bus<="ZZZZZZZZZZZZZZ";
If (SM_DIR = '1') then
nextstate<=E5;
End if;
When E5=>
-- Final set of data is retrived.........
mux_select <='1';
Reset_A<='0';
Reset_counter_b<='0';
Reset_counter_C<='0';
sel_14bit_mux <='0';
incrementB<='0';
output_signal <='0';
UBL <='0';
LBL <='0';
CE0 <='0';
CE1 <='1';
Output_Enable<='0';
Read_write <='1';
--Data_out_bus(13 downto 0) <= Address_bus(13 downto 0);
--Data_out_bus(18 downto 14)<=Address_bus(18 downto 14);
If (SM_DIR = '1') then
nextstate<=E6;
End if;
When E6=>
-- Waitng for the CPLD_Ready signal to out put 19 bits!!!
If (CPLD_READY ='1') Then
mux_select <='1';
Reset_A<='0';
Reset_counter_b<='0';
Reset_counter_C<='0';
sel_14bit_mux <='0';
incrementB<='0';
output_signal <='0';
UBL <='0';
LBL <='0';
CE0 <='0';
CE1 <='1';
Output_Enable<='0';
Read_write <='1';
--Data_out_bus(13 downto 0) <= "01010101010101";
--Data_out_bus(18 downto 14) <= "10101";
Data_out_bus(13 downto 0) <= Address_bus(13 downto 0);
If (SM_DIR = '1') then
nextstate<=E1;
End If;
Else
mux_select <='1';
Reset_A<='0';
Reset_counter_b<='0';
Reset_counter_C<='0';
sel_14bit_mux <='0';
incrementB<='0';
output_signal <='0';
UBL <='0';
LBL <='0';
CE0 <='0';
CE1 <='1';
Output_Enable<='0';
Read_write <='1';
If (SM_DIR = '1') then
nextstate<=E6;
End If;
End If;
When others =>
nextstate <= E1;
End Case;
End Process;
----------------------------------------
Process (DPR_CLK)
Begin
If (DPR_CLK'event And DPR_CLK='1') Then
State <= nextstate;
SM_DIR <= OE1;
End If;
End Process;
--------------Counter'C' Process----------------
PROCESS(equalsignalB)
Begin
If ( equalsignalB'event AND equalsignalB='0') then
State_G <= nextstate_G;
SM_DIR_G <= '1';
End If;
End Process;
---------Working area for the Counter C ( Sample Counter )----
PROCESS(State_G,nextstate_G,SM_DIR_G)
Begin
Case State_G is
When G0=>
If (SM_DIR_G='1') Then
incrementc <= '1';
nextstate_G <= G0;
End If;
When others =>
nextstate_G <= G0;
End Case;
End Process;
-----------Counter 'A' 14 bit counter process---
Process(equalsignalc)
Begin
If (equalsignalc'event AND equalsignalc='0') then
State_F <= nextstate_F;
SM_DIR_F <= '1';
End If;
End Process;
------------Working area for the counterA-----
PROCESS(State_F,nextstate_F,SM_DIR_F)
Begin
Case State_F is
When F0=>
If (SM_DIR_F='1') Then
inc <= '1';
nextstate_F <= F0;
End If;
When others =>
nextstate_F <= F0;
End Case;
End process;
------------------------------------------
End DPR_ARCH;
---------------------14 -bit counter (Frame
counter)-------------------
Library IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
Entity counter is
Port (
-- temp : out unsigned ( 3 downto 0);
Qout : out unsigned (13 downto 0);--:="11111111111111"; -- 19 bit
address bus output
--Din
ut unsigned (13 downto 0); -- 19 bit address bus inputCLK : in std_logic; -- Clock for the counter
P : in std_logic; -- Increment the count
count_equal: out std_logic;
Reset_c: in std_logic
);
End counter;
Architecture count_arch of counter is
Signal Q : unsigned (13 downto 0);
Signal D : unsigned (13 downto 0):="00000000000000";
Begin
--count_equal<=Q(1);
Process(Clk, Reset_c)
Begin
If (Reset_c = '1') then
-- count_equal <='0';
Q(13 downto 0) <= ('0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', '0' );
Qout<=Q;
Elsif (Clk='1' and Clk'event) then
If (P = '0') then
Q <= Q + 1;
Qout<=Q;
--count_equal <='0';
If(Q=D) Then
-- count_equal<='1';
Q(13 downto 0) <= ( '0', '0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0');
Qout<=Q;
End If;
End If;
--End If;
End if;
End process;
End count_arch ;
------------------14 bit Multiplexer----------------
Library IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
Entity multiplexer is
Port (
--its_clk : in std_logic;
Sel_line : in std_logic;
data_in_counter : in unsigned ( 13 downto 0);
data_in_data_bus : in unsigned ( 13 downto 0);
data_out_mux : out unsigned ( 13 downto 0)
);
End multiplexer;
Architecture muxq of multiplexer is
Begi
Process (Sel_line)
Begin
Case Sel_line is
When '1'=>
data_out_mux <= data_in_counter;
When '0'=>
data_out_mux <=data_in_data_bus;
When others =>
data_out_mux <="ZZZZZZZZZZZZZZ";
End case;
End process;
End muxq;
-----------5 bit counter------------------
Library IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
Entity counter_b is
Port (
Qout_b : out unsigned (4 downto 0 ); -- 19 bit address bus output
--Din_b : in unsigned (4 downto 0); -- 19 bit address bus input
CLK_b : in std_logic; -- Clock for the counter
Load_b : out std_logic; -- Load the intial count
CLRN_b : in std_logic; -- Reset the counter in the beginning
P_b : in std_logic; -- Increment the count
count_equal_b: out std_logic;
Reset_b: in std_logic
);
End counter_b;
Architecture count_arch_b of counter_b is
Signal get_equal_b: std_logic;
Signal Q_b : unsigned (4 downto 0);
Signal D_b : unsigned ( 4 downto 0):="00011";
Begin
count_equal_b<=Q_b(4);
--Load_b <= Q_b(4);
Process(CLK_b,Reset_b)
Begin
If ( Reset_b='1') Then
Q_b <= ('0', '0', '0', '0', '0');
Qout_b <= Q_b;
Load_b<='0';
Else If (CLK_b='1' and CLK_b'event) then
If (P_b='1') Then
Q_b<=Q_b +1;
Qout_b<= Q_b;
Load_b<='0';
If (Q_b= D_b) Then
Load_b<='1';
Q_b <= ('0', '0', '0', '0', '0');
Qout_b<= Q_b;
End If;
End If;
End if;
End If;
End process;
End count_arch_b ;
-------------5 bit multiplexer--------------
Library IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
Entity MUX is
Port (
counter_b_datain: in unsigned( 9 downto 5);
counter_c_datain: in unsigned( 9 downto 5);
Select_line: in std_logic;
Data_output : out unsigned ( 9 downto 5)
);
End MUX;
Architecture behav of MUX is
Begin
Process(Select_line)
Begin
Case Select_line is
When '1'=>
Data_output <= counter_c_datain;
When '0'=>
Data_output <= counter_b_datain;
When others=>
Data_output <= "00000";
End Case;
End process;
End behav;
-----X--------------X-------------------X---------------------------X-----------------