C
Chao
Guest
Anyone had used FPGA advantage with source code like
'include "../rtl/test_include.v"
even I added file test_include.v into the project, FPGA advantage still
can not find the parameters in the source code. It gives a bunch of
errors like
** Error: C:/test/chip2/user_io.v(59): (vlog-2163) Macro `dd_width is
undefined.
etc.
Anyone has experience on this? Thanks.
'include "../rtl/test_include.v"
even I added file test_include.v into the project, FPGA advantage still
can not find the parameters in the source code. It gives a bunch of
errors like
** Error: C:/test/chip2/user_io.v(59): (vlog-2163) Macro `dd_width is
undefined.
etc.
Anyone has experience on this? Thanks.