formatted data

[leaf]

Hi,

Is there a way to output a formatted data based on 3 input clocks?

I'll show you what i mean:

clk1, clk2, clk3 // input clocks
data_i // input data 1-bit
data_o // output data

now,
data_i will be set (0 or 1)
clk1, clk2, clk3 will arrive in different times
data_o will output based on clk1,clk2,clk3

here's an example: RTZ (Return to Zero) type

when clk1 arrives data_o gets the Value of data_i
when clk2 arrives data_o goes HIGH
when clk3 arrives data_o goes back to LOW

another example: SBC (Surrounded by complement) type

when clk1 arrives data_o gets the Value of not(data_i)
when clk2 arrives data_o gets the Value of data_i
when clk3 arrives data_o gets the Value of not(data_i)

---
leaf

 

[John_H]

If you're encoding a data stream, shouldn't there be 1 clock for the data
rate and simple control logic to generate the RZ or SbC data format?
Multiple clocks can make life a sincere mess.

"leaf" <adventleaf@gmail.com> wrote in message
news:1139258078.225499.232610@g43g2000cwa.googlegroups.com...

Hi,

Is there a way to output a formatted data based on 3 input clocks?

I'll show you what i mean:

clk1, clk2, clk3 // input clocks
data_i // input data 1-bit
data_o // output data

now,
data_i will be set (0 or 1)
clk1, clk2, clk3 will arrive in different times
data_o will output based on clk1,clk2,clk3

here's an example: RTZ (Return to Zero) type

when clk1 arrives data_o gets the Value of data_i
when clk2 arrives data_o goes HIGH
when clk3 arrives data_o goes back to LOW

another example: SBC (Surrounded by complement) type

when clk1 arrives data_o gets the Value of not(data_i)
when clk2 arrives data_o gets the Value of data_i
when clk3 arrives data_o gets the Value of not(data_i)

---
leaf

 

[leaf]

you mean i should create a state machine?

but i'm not making a "data stream"
the clocks that arrive are programmed in ns, they can even arrive on
same times if programmed to do so.

--
leaf

 

[John_H]

"leaf" <adventleaf@gmail.com> wrote in message
news:1139268093.680357.200230@g47g2000cwa.googlegroups.com...

you mean i should create a state machine?

but i'm not making a "data stream"
the clocks that arrive are programmed in ns, they can even arrive on
same times if programmed to do so.

--
leaf

If not a data stream, what are you trying to encode with Return to Zero or
with Surrounded by Complement coding?

And what clocks are you suggesting are "programmed in nanoseconds?" Are
those clocks used to encode the data? Is their source external to your
Verilog design? If internal to your Verilog design, figure out what
generates these "clocks" in the first place and you might see opportunity
for simple control. A 3-bit function seems a little simple to be considered
a state machine (since it's more like a state worm gear rather than a full
machine) but if you want to think of the control mechanism as such, please
do. The task is pretty small so the design of the logic should be straight
forward as long as the control signals are all nicely related to the "one"
clock that you want for your encoded... values.

Bottom line, manipulating registers with multiple clocks isn't pretty. How
do you decide what to do if the clock that says "go hi" comes in at the same
time as the clock that says "go low?" Registers in most hardware are
designed to change states on one clock edge. To get a simulation of more
than one clock, some tricks can be brought to bear to present a
combinatorial output of multiple registers (each clocked by different
source) but these approaches require explicit clock-to-clock timing
relationships (exclusion zones).

So. Just what are you trying to accomplish?