Formal Verification

[Gokul]

Can Someone please throw some light on the following Issues ???

What is "Formal Verification" ???

What is its Significance in Modernday Industry Verification
Environments ???

How widely it is used and How reliable it is With respect to Chip
Verification ???

What is the advantage that it holds when compared with Gate Level
Simulations(GLS) ???

I couldn't find some Good material on these to get clarified.It will
be great if someone point me to some good links or Publications ???

 

[Muzaffer Kal]

On Mon, 20 Oct 2008 03:07:17 -0700 (PDT), Gokul <gokul.bits@gmail.com>
wrote:

Can Someone please throw some light on the following Issues ???

What is "Formal Verification" ???

What is its Significance in Modernday Industry Verification
Environments ???

How widely it is used and How reliable it is With respect to Chip
Verification ???

What is the advantage that it holds when compared with Gate Level
Simulations(GLS) ???

I couldn't find some Good material on these to get clarified.It will
be great if someone point me to some good links or Publications ???

Start here: http://www.google.com/search?hl=en&q=formal+verification

Muzaffer Kal

ASIC/FPGA Design Services
DSPIA INC.
http://www.dspia.com