Forcing a value into multi-dimensional array (ModelSim)

[Jean-Christophe Rat]

Hello,

If I create 2 registers as follows...
reg [0:31] a_0;
reg [0:31] a_1;
.... I can force the value I want into a_0 or a_1 with ModelSim
simulator.

If I do the same with a multidimensional array...
reg [0:31] a[0:1];
.... I can't force anything into a[0] nor a[1].

I've always worked with VHDL before, and can't remember of any such
problem. Is this a Verilog specific issue?

Thanks for your help!

JC