Force statement question

[Phil Lide]

Project 1: vera + verilog + ncverilog:

I forced a reset input of a sub-block from vera using a verilog call.
The reset was applied to the sub-block only.

Project 2: system verilog + vcs

I forced a reset input of a sub-block from sv. The reset was applied
to the entire reset tree.

Can anyone tell me if this is a simulator issue or a verilog versus sv
issue?

TIA

Phil

 

[Utku Özcan]

Have you applied force to two different subblocks in each project or to
the same block in both? If different subblocks, then the reset can be
also different, dependent upon your design. In that case, if a subblock
receives a local reset, then force has a local effect also.

If a subblock has a "global" reset input, applying a local force
doesn't help. You must isolate the reset connection in hardware to get
the effect you want, because simulator will try to "explode" the force
thru global connectivity. I think this is a Verilog feature.

I recommend you should apply the forces in TCL scripts, to see in which
part is affected, because simulator will generate information about
force in TCL. If you embed force statements in Verilog it will be
difficult to debug the design.

Utku.

Phil Lide yazdi:

Project 1: vera + verilog + ncverilog:

I forced a reset input of a sub-block from vera using a verilog call.
The reset was applied to the sub-block only.

Project 2: system verilog + vcs

I forced a reset input of a sub-block from sv. The reset was applied
to the entire reset tree.

Can anyone tell me if this is a simulator issue or a verilog versus sv
issue?

TIA

Phil