P
py
Guest
In a testbench, let say we have a simple loop that assigns data and valid signals to a DUT's size 2 input array for NUM_CLK cycles, ex:
for ii in 0 to NUM_CLK-1 loop
for jj in 0 to 1 loop
valid(jj) <= '1';
data(jj) <= data_source(jj)(ii);
end loop;
wait for rising_edge(clk);
end loop;
My question is, what's the easiest way to introduce a delay offset between the valid and data stream in this format? To clarify, let say data_source for data(0) and data(1) are identical, a delay offset of 2 would make the waveform look like:
data(0) 0 0 F D F E F 0 0
valid(0) 0 0 1 1 1 1 1 0 0
data(1) 0 0 0 0 F D F E F
valid(1) 0 0 0 0 1 1 1 1 1
One way that I used, and kind of work is to factor in the offset into the loop structure, ex:
for ii in 0 to NUM_CLK-1+delay loop
if jj=1 then
--only assign signal when ii = delay, otherwise idle
end if;
....
But I want to know if there is a better solution out there. Ideally, I would like to not change the loop structure. So I was thinking about piping the input signal through some kind of intermediate function call or construct that would take care of the delay, like
delay(0) := 0;
delay(1) := 2;
for ii in 0 to NUM_CLK-1 loop
for jj in 0 to 1 loop
valid(jj) <= '1';
data(jj) <= magical_delay_function( data_source(jj)(ii), delay(jj));
end loop;
wait for rising_edge(clk);
end loop;
So the function would acts as a barrel shifter. Not sure if this is the right way to go.
Any thoughts into this will be appreciated. Thanks!
for ii in 0 to NUM_CLK-1 loop
for jj in 0 to 1 loop
valid(jj) <= '1';
data(jj) <= data_source(jj)(ii);
end loop;
wait for rising_edge(clk);
end loop;
My question is, what's the easiest way to introduce a delay offset between the valid and data stream in this format? To clarify, let say data_source for data(0) and data(1) are identical, a delay offset of 2 would make the waveform look like:
data(0) 0 0 F D F E F 0 0
valid(0) 0 0 1 1 1 1 1 0 0
data(1) 0 0 0 0 F D F E F
valid(1) 0 0 0 0 1 1 1 1 1
One way that I used, and kind of work is to factor in the offset into the loop structure, ex:
for ii in 0 to NUM_CLK-1+delay loop
if jj=1 then
--only assign signal when ii = delay, otherwise idle
end if;
....
But I want to know if there is a better solution out there. Ideally, I would like to not change the loop structure. So I was thinking about piping the input signal through some kind of intermediate function call or construct that would take care of the delay, like
delay(0) := 0;
delay(1) := 2;
for ii in 0 to NUM_CLK-1 loop
for jj in 0 to 1 loop
valid(jj) <= '1';
data(jj) <= magical_delay_function( data_source(jj)(ii), delay(jj));
end loop;
wait for rising_edge(clk);
end loop;
So the function would acts as a barrel shifter. Not sure if this is the right way to go.
Any thoughts into this will be appreciated. Thanks!