For SDRAM, is it ok to give it faster refresh rate than data

[news reader]

The datasheet says distributed refresh cycle of 15us.
In my FPGA design, there are periodic empty timing slots every 9us,
each slot can fit in a refresh cycle (100ns). Can I just use these slots
and refresh the SDRAM every 9us?

 

[Kai Harrekilde-Petersen]

"news reader" <newsreader@google.com> writes:

The datasheet says distributed refresh cycle of 15us.
In my FPGA design, there are periodic empty timing slots every 9us,
each slot can fit in a refresh cycle (100ns). Can I just use these slots
and refresh the SDRAM every 9us?

That should be perfectly OK. The refresh cycles are there to ensure
that all rows in the memory array are regularly read and written back
(the storage element is a leaky capacitor).


Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>

 

[news reader]

"Kai Harrekilde-Petersen" <khp@harrekilde.dk> wrote in message
news:umz1jgrq4.fsf@harrekilde.dk...

"news reader" <newsreader@google.com> writes:

The datasheet says distributed refresh cycle of 15us.
In my FPGA design, there are periodic empty timing slots every 9us,
each slot can fit in a refresh cycle (100ns). Can I just use these slots
and refresh the SDRAM every 9us?

That should be perfectly OK. The refresh cycles are there to ensure
that all rows in the memory array are regularly read and written back
(the storage element is a leaky capacitor).


Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk

Thank you!

 

[glen herrmannsfeldt]

Kai Harrekilde-Petersen wrote:

(someone wrote)

The datasheet says distributed refresh cycle of 15us.
In my FPGA design, there are periodic empty timing slots every 9us,
each slot can fit in a refresh cycle (100ns). Can I just use these slots
and refresh the SDRAM every 9us?

That should be perfectly OK. The refresh cycles are there to ensure
that all rows in the memory array are regularly read and written back
(the storage element is a leaky capacitor).

In years past it was popular to design systems with a video
display in DRAM, alternating cycles with the processor. Cycling
through the display memory does the refresh. If you manage to read
each row every (appropriate number) of milliseconds you don't
need any refresh (only) cycles.

-- glen

 

[gabor]

On Apr 13, 2:28 am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:

Kai Harrekilde-Petersen wrote:

(someone wrote)

The datasheet says distributed refresh cycle of 15us.
In my FPGA design, there are periodic empty timing slots every 9us,
each slot can fit in a refresh cycle (100ns). Can I just use these slots
and refresh the SDRAM every 9us?
That should be perfectly OK. The refresh cycles are there to ensure
that all rows in the memory array are regularly read and written back
(the storage element is a leaky capacitor).

In years past it was popular to design systems with a video
display in DRAM, alternating cycles with the processor. Cycling
through the display memory does the refresh. If you manage to read
each row every (appropriate number) of milliseconds you don't
need any refresh (only) cycles.

-- glen

This is true, but remember with multi-bank parts (all SGRAM, and
SDRAM) each
auto-refresh cycle does one row in all banks, while access to video
memory
will be one bank at a time. Thus you need to make sure that the video
addressing is set up to use all rows of all banks within the refresh
period.

Another fly in the ointment for DDR SDRAM parts is the JEDEC
requirement
for auto refresh cycles to allow delay-locked loop update. Most parts
I've used do not have this particular requirement, but it means a
design
without at least the minimum recommended auto-refresh rate will not be
compliant with the spec and therefore presumable not compliant with
some
actual parts.

Regards,
Gabor