Flyback power supplies, one last time

[Joel Kolstad]

While I've been muddling with software for a bit now, I went back and
re-read one of Terry Given's comments:

---

BTW, go look at what happens to your flyback converter when your first turn
it ON. switch turns on at max. D, charging L up to Ipk (or thereabouts),
dIprim/dt = Vprim/Lprim. During flyback, energy dumps into UNCHARGED output
capacitor Cout through diode D. dIsec/dt = Vsec/Lsec = (Vout+Vd)/Lsec BUT
Vout = 0 so dI/dt is MUCH less than you expected. Therefore only a small
amount of energy gets dumped in Cout, the rest stays in Lsec (low dIsec/dt
means it doesnt discharge very rapidly). When your switch NEXT turns on, Ip
starts off at close to Ipeak, NOT zero. Eventually Cout charges to Vout, and
dIp/dt = dIs/dt (or thereabouts)

If you do not have a dedicated peak current trip, and instead have a fixed
duty cycle, you WILL blow up your smps...

---

Great, I appreciate this and can deal with it. But tell me... I'm looking
at Abraham Pressman's book (where all the controllers are continuous time
devices) under the section, "4.3.4. Flyback Disadvantages," and he makes no
mention of this problem! Rather odd, no? Why is this apparently not always
a problem with traditional designs? Seems like they'd immediately blow up
too.

Thanks,
---Joel

 

[Fritz Schlunder]

"Joel Kolstad" <JKolstad71HatesSpam@Yahoo.Com> wrote in message
news:c98990$6v2$1@news.oregonstate.edu...

While I've been muddling with software for a bit now, I went back and
re-read one of Terry Given's comments:

---

BTW, go look at what happens to your flyback converter when your first
turn
it ON. switch turns on at max. D, charging L up to Ipk (or thereabouts),
dIprim/dt = Vprim/Lprim. During flyback, energy dumps into UNCHARGED
output
capacitor Cout through diode D. dIsec/dt = Vsec/Lsec = (Vout+Vd)/Lsec BUT
Vout = 0 so dI/dt is MUCH less than you expected. Therefore only a small
amount of energy gets dumped in Cout, the rest stays in Lsec (low dIsec/dt
means it doesnt discharge very rapidly). When your switch NEXT turns on,
Ip
starts off at close to Ipeak, NOT zero. Eventually Cout charges to Vout,
and
dIp/dt = dIs/dt (or thereabouts)

If you do not have a dedicated peak current trip, and instead have a fixed
duty cycle, you WILL blow up your smps...

---

Great, I appreciate this and can deal with it. But tell me... I'm looking
at Abraham Pressman's book (where all the controllers are continuous time
devices) under the section, "4.3.4. Flyback Disadvantages," and he makes
no
mention of this problem! Rather odd, no? Why is this apparently not
always
a problem with traditional designs? Seems like they'd immediately blow up
too.

Thanks,
---Joel

Well I don't have the above referenced book to look at, but this basic
problem isn't just limited to the flyback topology. Terry Given's comments
are correct although I think the "WILL" (blow up your smps) shouldn't
necessarily be capitalized.

In any switch mode powersupply topology or even linear regulator for that
matter start up can be quite stressful. Initially the output capacitors are
uncharged and therefore look like a short circuit. Whether the main
switching element (normally the weakest power element in an SMPS) or pass
transistor fails on power on or not depends upon the relative
voltages/impedances/output capacitor energy storage/and transistor
ruggedness. In a low input voltage converter (IE: 12V or less) with only
modest output capacitance values (IE: <1 joule total storage), the main
power switch will not usually fail. Even in these types of converters it is
wise to use some form of soft start and/or peak current limiting, but
usually one can skimp on this and won't find any immediate failure problems
(though in the long run reliability may still be compromised)... Staying
within the switching element's published safe operating curves is very
important...

On the other hand when you start playing with mains voltages (IE: 160V) and
beyond with output capacitances storing decent amounts of energy (IE: > ~0.5
Joule), some form of peak current limiting is pretty much absolutely
mandatory for any kind of remotely reliable design.

If this isn't covered somewhere in Abraham Pressman's book I would venture
to claim the book isn't complete.

 

[legg]

On Fri, 28 May 2004 14:03:17 -0700, "Joel Kolstad"
<JKolstad71HatesSpam@Yahoo.Com> wrote:

Great, I appreciate this and can deal with it. But tell me... I'm looking
at Abraham Pressman's book (where all the controllers are continuous time
devices) under the section, "4.3.4. Flyback Disadvantages," and he makes no
mention of this problem! Rather odd, no? Why is this apparently not always
a problem with traditional designs? Seems like they'd immediately blow up
too.

Start-up and transient behaviours are not inherently characteristics
of any topology - they are a side-effect of the application.

The use of an effective slow-start or compensation for other
large-scale or fault conditions in an application, is a decision left
to the designer. In the case you mention, it is the potentially
defective response of a specific control method application that might
give problems, not the single flyback topology used as an example.

If a fault is going to occur every time power is applied, it is
unlikely to be missed. More of a problem are those faults that don't
give obvious symptoms. If you examine your circuit critically for it's
response to a full schedule of single-fault abnormal test conditions,
you will get a pretty good idea as to it's general ruggedness.

The flyback primary is actually extremely well-isolated from the
output for most fault conditions. This comes at the expense of the
loss of the reflected output current sensing, normally possible with a
more closely-coupled topology. Simply limiting primary current in a
flyback will not guarantee prevention of component damage due to
excess secondary current, in the event of secondary overload.

Sensible application of proven technology is always the responsibility
of the designer.

RL

 

[Joel Kolstad]

Fritz Schlunder <me@privacy.net> wrote:

Well I don't have the above referenced book to look at, but this basic
problem isn't just limited to the flyback topology. Terry Given's
comments are correct although I think the "WILL" (blow up your smps)
shouldn't necessarily be capitalized.

In any switch mode powersupply topology or even linear regulator for that
matter start up can be quite stressful. Initially the output capacitors
are uncharged and therefore look like a short circuit.

One of the reason I'm playing with the flyback topology at the moment is
that it seems relatively 'gentle' in terms of moving energy around... the
primary gets loaded up with energy that's then dumped into the secondary,
and even if the secondary is shorted, the primary side doesn't 'see' that
fact directly. (Shorting the secondary seems as though it puts the flyback
back into the startup position -- the output voltage is close to zero, so
the secondary actually can't extract energy from the transformer quickly at
all.)

In a low input voltage converter (IE: 12V or less) with only
modest output capacitance values (IE: <1 joule total storage), the main
power switch will not usually fail. Even in these types of converters it
is wise to use some form of soft start and/or peak current limiting

I'm using the 'soft start' approach. I'm glad I'm starting with a 25W, 12V
input design... I think. I do know that with my design if you saturate
the transformer it starts making scary noises but I can then switch it off
before anything is permanently damaged.

If this isn't covered somewhere in Abraham Pressman's book I would venture
to claim the book isn't complete.

He's a big fan of current mode converters for anything other than low power
designs, so I imagine he's well aware of these issues but was probably
already 'over budget' at over 2" worth of pages!

Some years back I had one of those (cheap) 12V->120V inverters rated at 100W
that I smoked while asking it for no more than some 50-70W (it was powering
a small laptop computer). I wasn't impressed with that design, but I figure
that for the $40 or whatever it was I got what I paid for.

---Joel

 

[Terry Given]

"legg" <legg@nospam.magma.ca> wrote in message
news:46dfb0913guivs9dc6albjea2uhmq7q6ae@4ax.com...

On Fri, 28 May 2004 14:03:17 -0700, "Joel Kolstad"
JKolstad71HatesSpam@Yahoo.Com> wrote:

Great, I appreciate this and can deal with it. But tell me... I'm
looking
at Abraham Pressman's book (where all the controllers are continuous time
devices) under the section, "4.3.4. Flyback Disadvantages," and he makes
no
mention of this problem! Rather odd, no? Why is this apparently not
always
a problem with traditional designs? Seems like they'd immediately blow
up
too.

Start-up and transient behaviours are not inherently characteristics
of any topology - they are a side-effect of the application.

The use of an effective slow-start or compensation for other
large-scale or fault conditions in an application, is a decision left
to the designer. In the case you mention, it is the potentially
defective response of a specific control method application that might
give problems, not the single flyback topology used as an example.

If a fault is going to occur every time power is applied, it is
unlikely to be missed. More of a problem are those faults that don't
give obvious symptoms. If you examine your circuit critically for it's
response to a full schedule of single-fault abnormal test conditions,
you will get a pretty good idea as to it's general ruggedness.

The flyback primary is actually extremely well-isolated from the
output for most fault conditions. This comes at the expense of the
loss of the reflected output current sensing, normally possible with a
more closely-coupled topology. Simply limiting primary current in a
flyback will not guarantee prevention of component damage due to
excess secondary current, in the event of secondary overload.

Sensible application of proven technology is always the responsibility
of the designer.

RL

As usual, great points from Legg. A trivial example proves his last point:
consider a dual-output flyback - 10W at 5V, 1W at 12V. now short-circuit the
12V supply. watch all the transformer energy now flow into the puny 12V
rectifier (1N4148), not the monster 5V rectifier (which must handle about 8A
peak, every cycle).

Inductor saturation is most likely to cause Joel catastrophic problems - his
duty cycle is fixed, based on the assumption that it operates in DCM. When
it doesnt, the primary current increases by roughly Ipk_nom every on time,
and hardly decreases at all during the off time. If the switch can provide
enough current (say a FET) then the inductor will eventually saturate, at
which point the primary current rises rapidly (if you have a gap in the
inductor, the new dIp/dt will be le/lg where le is effective path length of
core, lg = gap spacing - in other words, the inductor now behaves as if air
cored). usually the new dI/dt is so high that the current ends up limited by
the series R (or beta limiting with a bipolar, or 10xIrated with an IGBT)
and the switch goes BANG.

peak primary power limiting can stop this (if you do it well) but as Legg
pointed out, that wont necessarily save your circuit from other problems. I
have dealt with this in the past using digital soft-starting (pld/micro
ramps up D from 0 to setpoint over some time) in conjunction with feeble
transistor drive (and a big enough junction to soak up the watts). Making
sure the transformer doesnt saturate too soon is a good start, too. You know
its a good design when it can run continuously from Vinmax at Tmax into a
dead short on any output, without failure, and run correctly once the short
is removed. some smps chips have 2x current comparators - the usual PCMC
comparator, and one set about 20% higher that is the "oh shit" comparator,
and usually triggers hiccup-mode shutdown/auto-restart operation.

Joel, in theory you could measure Vout, and knowing Vd, Ls calculate dIs/dt
and reflect that back to work out your duty cycle - thereby always choosing
the duty cycle that enables all energy stored in the core during Ton to be
dumped into the core during Toff. This would automatically deal with an
output short-circuit. In practice whether or not it works depends entirely
on your sampling time, not the PWM frequency - because you have 0-1 sample
times before anything can be observed (worst case events always happen just
after you sample the ADCs . add in the time to do the calc and output the
new duty cycle (often a whole sample time, but can be quite quick) and you
will see that these numbers are what determines xfmr saturation. IIRC your
sample rate aint too fast.

Why didnt Pressman talk about it? I can think of lots of reasons. Firstly if
you use PCMC (and virtually everyone does), it will automatically limit the
peak primary current (and usually therefore power). This reason alone is
often enough justification to use PCMC - the primary of a converter usually
has more energy available to destroy things in the event of a fault (esp.
with off-line smps), unlike the secondary. so preventing the primary from
failing is usually a good way to prevent catastrophic damage when things do
go wrong. Its also a big book, with lots of goodies. room or time
constraints? quite possible.

real psu's usually have soft starting, too. then again, cheap taiwanese crap
smps (like the NZ $25 "200W" smps I used to put into videogames) typically
dont. And they also periodically blow up when you turn them on (actually one
of the more common failures with el-cheapos is the rectifier diodes blow up
trying to charge the DC bus cap, as their Ifsm isnt big enough). The cheaper
the smps, the greater the likelihood it will go bang when you short its
output (PC repair guys are a great source of cheap heatsinks etc. as pc smps
crap out all the time - they usually will give you boxloads of dead ones

And of course it is precisely these "unusual" conditions that differentiate
the bad "designs" from the good ones. After I designed my first flyback with
built-in self destruct and found this issue (my smps actually blew up
because of a sneaky snubbing trick I pulled that required DCM), I got into
the habit of building smps-testers that power-cycle the unit at full load -
using a timer and relay to turn mains on and off (and discharge Cbus, Cout
when off. yay for multi-pole relays). Do that about once a minute, and leave
it running until it fails (or you leave the company a few years later) -
thats about 1440 starts/day, which is (usually) at least 100x greater than
the unit will see in practice, so its easy to do a "lifetime" test (10 yrs =
3650 days/100 = 3.65 days of accelerated testing). This is how mains gear is
tested (often with a plastic "finger" that pushes the switch. a million
times.

Cheers
Terry

 

[Joel Kolstad]

Thanks for all the feedback, guys. I see now that the idea of a 'pure
software' feedback loop is really quite limiting when it comes to preventing
catastrophic failures. I'll try Terry's test of cycling a dead short and
see what happens... I'm guessing that either my fuse will blow (hopefully)
or the main switch will (oops -- followed shortly thereafter by the fuse if
it fails short-circuit). I'm also a little concerned about what happens
when I go from full load to zero load -- will the feedback loop react
quickly enough to prevent my ~300V rail from shooting up over the voltage
ratings of the various secondary side devices before something croaks?
(It's a 400V capacitor and 600V rectifier.)

Joel, in theory you could measure Vout, and knowing Vd, Ls calculate
dIs/dt and reflect that back to work out your duty cycle - thereby always
choosing the duty cycle that enables all energy stored in the core during
Ton to be dumped into the core during Toff.

I'm thinking of doing something a little cruder whereby a lookup table is
used that limits the maximum duty cycle regardless of what the feedback loop
would like to do. This will inherently generate soft-start as well, I
believe.

This would automatically deal
with an output short-circuit. In practice whether or not it works depends
entirely on your sampling time...

I've been planning to increase it... up to about 10kHz; above that I'd have
serious concerns about whether or not I'd have enough time to process each
sample. That's still 5 switching cycles per ADC sample, though.

---Joel

 

[analog]

Joel Kolstad wrote:

While I've been muddling with software for a bit now, I went back and
re-read one of Terry Given's comments:

---

BTW, go look at what happens to your flyback converter when your first turn
it ON. switch turns on at max. D, charging L up to Ipk (or thereabouts),
dIprim/dt = Vprim/Lprim. During flyback, energy dumps into UNCHARGED output
capacitor Cout through diode D. dIsec/dt = Vsec/Lsec = (Vout+Vd)/Lsec BUT
Vout = 0 so dI/dt is MUCH less than you expected. Therefore only a small
amount of energy gets dumped in Cout, the rest stays in Lsec (low dIsec/dt
means it doesnt discharge very rapidly). When your switch NEXT turns on, Ip
starts off at close to Ipeak, NOT zero. Eventually Cout charges to Vout, and
dIp/dt = dIs/dt (or thereabouts)

If you do not have a dedicated peak current trip, and instead have a fixed
duty cycle, you WILL blow up your smps...

---

Great, I appreciate this and can deal with it. But tell me... I'm looking
at Abraham Pressman's book (where all the controllers are continuous time
devices) under the section, "4.3.4. Flyback Disadvantages," and he makes no
mention of this problem! Rather odd, no? Why is this apparently not always
a problem with traditional designs? Seems like they'd immediately blow up
too.

One low parts count way to prevent short circuit runaway is to make the
flyback's operating frequency inversely dependent on output voltage.
With a UC384X based design, the oscillator capacitor is normally charged
via a resistor to Vref (5V). Usually there is a small slave flyback
winding to provide nominal 12 volt power to the PWM IC. A shorted output
is reflected to this voltage. If a large enough percentage of the PWM
IC's oscillator charging current is feed from an additional resistor to the
slave 12 volts, then a shorted output can result in enough off time for
flyback current to ramp to zero. A practical implementation usually takes
a few more parts than I've indicated here, but the idea is the same.

analog

 

[legg]

On Fri, 28 May 2004 19:31:53 -0700, "Joel Kolstad"
<JKolstad71HatesSpam@Yahoo.Com> wrote:

Thanks for all the feedback, guys. I see now that the idea of a 'pure
software' feedback loop is really quite limiting when it comes to preventing
catastrophic failures. I'll try Terry's test of cycling a dead short and
see what happens... I'm guessing that either my fuse will blow (hopefully)
or the main switch will (oops -- followed shortly thereafter by the fuse if
it fails short-circuit). I'm also a little concerned about what happens
when I go from full load to zero load -- will the feedback loop react
quickly enough to prevent my ~300V rail from shooting up over the voltage

SW control brings up the hairy question of housekeeping power. This is
the Abbott and Costello side of power conversion.

"Who's 'on', first?"

In circuits where logic or control power is obtained from a low-power
auxiliary on the main transformer, the shutdown can be enforced by
simple collapse of the supply voltage. The output voltage collapse in
a flyback load can be crudely represented by the loss of reflected
flyback voltage in all coupled windings.

Your control circuit should be prepared to re-initialize safe
operation, following the passing of each 'undervoltage' event. This
could simply mean getting a PIC with a good UVreset, low power
consumption and a reliably starting oscillator.

Obviously, while this is happening, any 'protection' functions in the
hardware has to be the natural result of analog control sections.

Control circuitry that won't run off the same power as everything else
in the box, without a very good reason, is an offense in the eyes of
your creator.

RL

 

[Joerg]

Hi Joel,

Here I side with Terry and even all my low power SMPS designs have been
current mode controlled. No exceptions.

The point he brought up regarding unintended transfer from DCM to CCM
was once illustrated with sparks and kaboom: I redesigned a client's
system from Thevenin termination (a.k.a. space heaters) to AC
termination. The not so intended consequence was that the power
consumption became so low that the fixed duty cycle SMPS obviously
didn't want to stay in DCM. A squeal, then it started screaming, smoke
billowed and then it produced an impressive pyrotechnic showdown. All
within very few seconds, not enough to run to the back of the unit and
pull the breaker.

Regards, Joerg

http://www.analogconsultants.com

 

[Terry Given]

"Joel Kolstad" <JKolstad71HatesSpam@Yahoo.Com> wrote in message
news:c98sgv$fu1$1@news.oregonstate.edu...

Thanks for all the feedback, guys. I see now that the idea of a 'pure
software' feedback loop is really quite limiting when it comes to
preventing
catastrophic failures. I'll try Terry's test of cycling a dead short and
see what happens... I'm guessing that either my fuse will blow (hopefully)
or the main switch will (oops -- followed shortly thereafter by the fuse
if
it fails short-circuit). I'm also a little concerned about what happens
when I go from full load to zero load -- will the feedback loop react
quickly enough to prevent my ~300V rail from shooting up over the voltage
ratings of the various secondary side devices before something croaks?
(It's a 400V capacitor and 600V rectifier.)

good thought. when in doubt, sample faster.

Joel, in theory you could measure Vout, and knowing Vd, Ls calculate
dIs/dt and reflect that back to work out your duty cycle - thereby
always
choosing the duty cycle that enables all energy stored in the core
during
Ton to be dumped into the core during Toff.

I'm thinking of doing something a little cruder whereby a lookup table is
used that limits the maximum duty cycle regardless of what the feedback
loop
would like to do. This will inherently generate soft-start as well, I
believe.

doing 32-bit fixed point DSP with 24-bit mantissa, I used small LUTs to
calculate sin(x), atan(x), 1/sqrt(x) etc in 8 cycles, accurate to +/- 1/2
LSB. so much for crude.....

This would automatically deal
with an output short-circuit. In practice whether or not it works
depends
entirely on your sampling time...

I've been planning to increase it... up to about 10kHz; above that I'd
have
serious concerns about whether or not I'd have enough time to process each
sample. That's still 5 switching cycles per ADC sample, though.

---Joel

almost do-able. pretty easy to stop L from saturating. a decent size
junction on your switch to suckup the transient power, and it may well work.
The real trick is to figure out the necessary tests to PROVE it does go. Get
a faster micro.....

cheers
Terry

 

[Terry Given]

"analog" <analog@ieee.org> wrote in message
news:40B7F90B.DB0F0795@ieee.org...

Joel Kolstad wrote:

While I've been muddling with software for a bit now, I went back and
re-read one of Terry Given's comments:

---

BTW, go look at what happens to your flyback converter when your first
turn
it ON. switch turns on at max. D, charging L up to Ipk (or thereabouts),
dIprim/dt = Vprim/Lprim. During flyback, energy dumps into UNCHARGED
output
capacitor Cout through diode D. dIsec/dt = Vsec/Lsec = (Vout+Vd)/Lsec
BUT
Vout = 0 so dI/dt is MUCH less than you expected. Therefore only a small
amount of energy gets dumped in Cout, the rest stays in Lsec (low
dIsec/dt
means it doesnt discharge very rapidly). When your switch NEXT turns on,
Ip
starts off at close to Ipeak, NOT zero. Eventually Cout charges to Vout,
and
dIp/dt = dIs/dt (or thereabouts)

If you do not have a dedicated peak current trip, and instead have a
fixed
duty cycle, you WILL blow up your smps...

---

Great, I appreciate this and can deal with it. But tell me... I'm
looking
at Abraham Pressman's book (where all the controllers are continuous
time
devices) under the section, "4.3.4. Flyback Disadvantages," and he makes
no
mention of this problem! Rather odd, no? Why is this apparently not
always
a problem with traditional designs? Seems like they'd immediately blow
up
too.

One low parts count way to prevent short circuit runaway is to make the
flyback's operating frequency inversely dependent on output voltage.
With a UC384X based design, the oscillator capacitor is normally charged
via a resistor to Vref (5V). Usually there is a small slave flyback
winding to provide nominal 12 volt power to the PWM IC. A shorted output
is reflected to this voltage. If a large enough percentage of the PWM
IC's oscillator charging current is feed from an additional resistor to
the
slave 12 volts, then a shorted output can result in enough off time for
flyback current to ramp to zero. A practical implementation usually takes
a few more parts than I've indicated here, but the idea is the same.

analog

Nice. Just filter the piss out of it (break R into 2 parts, with cap
inbetween), lest problems arise - dunno if they will, but poor decoupling on
5Vref is usually a good way to cause problems, so feeding ac @ Fswitch back
into osc might not be a good idea

Cheers
Terry