Flops as synchronizers

[Paul Richardson]

In a design I a working on we use some flops as synchronizers, the verilog
models of these flops include $setuphold statements for checking the ck /d
input relationships. In the design, we have signals which do in fact violate
the setup/hold parameters of this flop. Since I am using it as a
synchronizer I figured I could just set the sdf information for setup and
hold to 0. However I notice that I still get a warning for a setup violation
AND the !Q output of the flop still goes to X.

Is there another way to do this, am I missing something ?

 

[Muzaffer Kal]

On Tue, 27 Jan 2004 22:25:14 GMT, Paul Richardson
<prich@earthlink.net> wrote:

In a design I a working on we use some flops as synchronizers, the verilog
models of these flops include $setuphold statements for checking the ck /d
input relationships. In the design, we have signals which do in fact violate
the setup/hold parameters of this flop. Since I am using it as a
synchronizer I figured I could just set the sdf information for setup and
hold to 0. However I notice that I still get a warning for a setup violation
AND the !Q output of the flop still goes to X.

Is there another way to do this, am I missing something ?

What you're trying to do should work and do what you want. I am
assuming you are making a mistake in zero-ing out the right slot in
SDF file. Check the timing report carefully in terms of which flop is
being reported and whether rising setup or falling setup is being
reported. Check whether you're really clearing the right flop's timing
values (do you have, by any chance, two flops by the same name at
different hierarchies or with very similar names ?)

Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations

 

[Paul Richardson]

On 1/27/04 8:37 PM, in article atee10tsergoi7ratu0qpou0e22gaiaiv7@4ax.com,
"Muzaffer Kal" <kal@dspia.com.deletethis> wrote:

On Tue, 27 Jan 2004 22:25:14 GMT, Paul Richardson
prich@earthlink.net> wrote:

In a design I a working on we use some flops as synchronizers, the verilog
models of these flops include $setuphold statements for checking the ck /d
input relationships. In the design, we have signals which do in fact violate
the setup/hold parameters of this flop. Since I am using it as a
synchronizer I figured I could just set the sdf information for setup and
hold to 0. However I notice that I still get a warning for a setup violation
AND the !Q output of the flop still goes to X.

Is there another way to do this, am I missing something ?

What you're trying to do should work and do what you want. I am
assuming you are making a mistake in zero-ing out the right slot in
SDF file. Check the timing report carefully in terms of which flop is
being reported and whether rising setup or falling setup is being
reported. Check whether you're really clearing the right flop's timing
values (do you have, by any chance, two flops by the same name at
different hierarchies or with very similar names ?)

Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm
implementations
I've gone back into the sdf and checked that I zero'ed out the right values

for the flop in question, as best as I can tell I think so. Sigh...

 

[Jerry]

"Paul Richardson" <prich@earthlink.net> wrote in message
news:BC3D438A.206A%prich@earthlink.net...

On 1/27/04 8:37 PM, in article atee10tsergoi7ratu0qpou0e22gaiaiv7@4ax.com,
"Muzaffer Kal" <kal@dspia.com.deletethis> wrote:

On Tue, 27 Jan 2004 22:25:14 GMT, Paul Richardson
prich@earthlink.net> wrote:

In a design I a working on we use some flops as synchronizers, the
verilog
models of these flops include $setuphold statements for checking the ck
/d
input relationships. In the design, we have signals which do in fact
violate
the setup/hold parameters of this flop. Since I am using it as a
synchronizer I figured I could just set the sdf information for setup
and
hold to 0. However I notice that I still get a warning for a setup
violation
AND the !Q output of the flop still goes to X.

Is there another way to do this, am I missing something ?

What you're trying to do should work and do what you want. I am
assuming you are making a mistake in zero-ing out the right slot in
SDF file. Check the timing report carefully in terms of which flop is
being reported and whether rising setup or falling setup is being
reported. Check whether you're really clearing the right flop's timing
values (do you have, by any chance, two flops by the same name at
different hierarchies or with very similar names ?)

Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm
implementations
I've gone back into the sdf and checked that I zero'ed out the right
values
for the flop in question, as best as I can tell I think so. Sigh...

Maybe you could modify your test bench and make those signals synchronous to

the flops.
BUT my signals are async in real life you say, yea but your flops have setup
and hold requirements I say.

I'm pretty sure this has come up in the past on this group. I thought the
solution was exactly what you did, hack the sdf.
You may want to hack the model of the flop and really fix it so those xxx's
don't get into the sims.

Jer

 

[Alexander Gnusin]

On Tue, 27 Jan 2004 22:25:14 GMT, Paul Richardson
prich@earthlink.net> wrote:

In a design I a working on we use some flops as synchronizers, the verilog
models of these flops include $setuphold statements for checking the ck /d
input relationships. In the design, we have signals which do in fact violate
the setup/hold parameters of this flop. Since I am using it as a
synchronizer I figured I could just set the sdf information for setup and
hold to 0. However I notice that I still get a warning for a setup violation
AND the !Q output of the flop still goes to X.

Is there another way to do this, am I missing something ?

You may consider to automatically identify cross-domain flops in
Synopsys DC or Primetime and then use "set_annotated_delay" command to
force setuphold of these flops to 0. Then, you don't need to manually
correct extracted SDF.

Regards,
Alexander Gnusin

 

[Kim Enkovaara]

Paul Richardson wrote:

the setup/hold parameters of this flop. Since I am using it as a
synchronizer I figured I could just set the sdf information for setup and
hold to 0. However I notice that I still get a warning for a setup violation
AND the !Q output of the flop still goes to X.

Is there another way to do this, am I missing something ?

There are also simulator dependent ways to fix the problem, they remove the need for SDF hacking. At least with multi gigabyte SDFs even editing of them becomes very difficult. I would love to find a good SDF editor that can show the hierarchy, search cells and show easily all rules in a cell etc. and also work with multi gigabyte files.

For example in Modelsim there is tcheck_set command that can be used to set single instances to disregard timing checks and X-propagation from the checks. Another easier trick in Modelsim is to use +no_notifier command line switch. After that X is not propagated anywhere. But after that you have to understand every single timing warning, and you won't get design full of X telling that some timing went wrong.

ps. Modelsim is not anymore a toy in netlist simulation as many people think. Newest versions beat VCS and NC-Verilog in huge designs easily. I have seen speedups up to 10x.

--Kim