Floorplanning techniques

[richie singh]

Hi,
I recently started working with FPGAs and am would like to learn about
floorplanning techniques. Could someone point me to documents or
design guides dealing with what issues should be kept in mind while
floorplanning a complex design..
Thanks to all who reply!!
R.B.

 

[Muthu]

Hi,

For FPGAs, the Vendor tools will do the the floor planning job in a
better way. You no need to spend time on that. All you need to know,
how to constraint the tool to make them to do what you want exactly.

like clock frequency, Input setup-hold, Output setup-hold and so on...
with this; tool will place the logics to acheive your timing
requiement.


Regards,
Muthu



richieb@rediffmail.com (richie singh) wrote in message news:<a0238c18.0312041811.56cc43d9@posting.google.com>...

Hi,
I recently started working with FPGAs and am would like to learn about
floorplanning techniques. Could someone point me to documents or
design guides dealing with what issues should be kept in mind while
floorplanning a complex design..
Thanks to all who reply!!
R.B.

 

[richie singh]

richieb@rediffmail.com (richie singh) wrote in message news:<a0238c18.0312041811.56cc43d9@posting.google.com>...

Hi,
I recently started working with FPGAs and am would like to learn about
floorplanning techniques. Could someone point me to documents or
design guides dealing with what issues should be kept in mind while
floorplanning a complex design..
Thanks to all who reply!!
R.B.

Muthu,
Thanks for your reply. I am interested in floorplanning because there
can be a scenario where the tool will not be able to meet timing and
manual effort will be involved in floorplanning. In such a case what
type of issues need to be kept in mind. Thanks!!
R.B

 

[Vinh Pham]

R.B.

Yeah ideally you'd like to solve your problem by setting up constraints to
guide the tools, because your floorplanning work is more likely to be wasted
if your design changes significantly enough (though creating relative
placement macros for sub blocks of your design can help preserve your work).
Area constraints, as opposed to timing constraints, can be helpful in
nudging the tools to placing smarter.

Of course, like you said, the tools might not have enough smarts to do what
you want or it might take too long to place/route without some intervention.

As far as floorplanning, the main thing is is to understand the layout of
the routing resources in your target FPGA. Xilinx's Spartan-III, for
example, has direct lines (that connect adjacent CLBs), double lines (that
connect every other), hex lines (which don't connect every 6 but every 3),
and long lines (which do connect every 6). So from best to least, you want
logic in: 1) the same CLB, 2) adjecent CLB, 3) two CLBs away, 4) three CLBs
away, or 5) six CLBs away. Four and five CLBs away could be worse than six.

A lot of times I find that when I floorplan I'm fixing some crazy things the
tools have done. Like for some reason the tools will take a 32-bit register
and instead of keeping it in order, it'll mix it up in a seemingly random
fashion.

They seemed to have architected their FPGAs for data to flow horizontally,
so keep that in mind. I'm not sure if it matters, but I always go
left-to-right because it feels natural.

Heh sorry I don't have too many pointers. I try not to floorplan (unless I
want to veg out. I find Xilinx's Floorplanner relaxing, it uses pretty
colors) and it feels more like an intuitive art than a science. One thing
you can try is to compile your design with only the difficult logic and the
other logic removed. This will help speed up the floorplan-route-results
cycle which sometimes can be more productive than trying to plan everything
up front, especially when we don't have a good knowledge of the routing or
we have the wrong ideas.

Best of luck,
Vinh

 

[Martin Euredjian]

"Muthu" wrote:

For FPGAs, the Vendor tools will do the the floor planning job in a
better way.

Well ... first of all, the tools don't floorplan. At all. They simply
place and route the logic for a design in order to meet whatever constraints
you specify. Floorplanning, from my vantage point, involves (and requires)
a higher level of thinking than what these tools can provide.

There have been many discussions on this N.G. about this. Hands down, if
you know what you are doing you can squeeze gobs more performance out of a
smaller and cheaper device than the tools seem to be able to deliver.
Floorplanning might also involve knowledge that the tools would not have
purely from timing constraints, like "my dev board has a two million gate
device but the product will have a 500K".

Again, discussed extensively here, the pushbutton approach doesn't tend to
do a good job aligning data paths and getting creative about layout. All
you have to do is start getting into building RPM's to realize how bad it
can get (when you compare to pushbutton) even in small test designs.

Also, floorplanning might be absolutely necessary for certain design flows.


The bottom line is that the pushbutton approach does not floorplan at all,
that still requires a human brain with more than one neuron firing.

The good news is that a properly constrained design is very likely to work
well via pushbutton these days. I would imagine that most designers out
there don't get into floorplanning and RPM's at all. It is only when you
want (or need) to push some limit (area, speed, device migration, etc.) that
playing in deeper water is the only way to go.


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"

 

[Philip Freidin]

richieb@rediffmail.com (richie singh) wrote in message news:<a0238c18.0312041811.56cc43d9@posting.google.com>...

Hi,
I recently started working with FPGAs and am would like to learn about
floorplanning techniques. Could someone point me to documents or
design guides dealing with what issues should be kept in mind while
floorplanning a complex design..
Thanks to all who reply!!
R.B.

Somewhat dated, but at least a start:

http://www.fliptronics.com/floorplanning1.html

Philip




Philip Freidin
Fliptronics

 

[MS]

If you are considering floorplanning- consider a physical synthesis
tool such as Amplify or Precision Physical Synthesis. It lets you
floorplan closer to the RTL- so it is easier to understand. Search
the board for more info.

Also- you should consider the backend tool that you are using. These
backend tools are getting better all the time. For example, the
latest version of Foundation (6.1 I believe) will do a far better job
that the version 4 I used to use. So when looking back at posts- keep
that in mind.