Floorplanning, Routing, FPGA Editor

  • Thread starter Martin Euredjian
  • Start date
M

Martin Euredjian

Guest
In wanting to gain a greater understanding of routing options (particularly
as related to making floorplanning decisions) I find myself studing devices
in the FPGA Editor. One question that occured to me is: How accurate a
representation of the actual device layout does this tool provide? Example:

I'm looking at an XC2V100-4FG456. I see that all embedded multipliers have
the I/O on the left side only. Obviously all PIP's are on that side as
well. And there are four switch boxes that would seem to be the best place
to connect in/out of the multipler. These switch boxes, in turn, would be
the way to access the CLB's to the immediate left and right(through their
own switch boxes). Double interconnect lines seem to be the best possible
path.

Are these accurate representations of the geometry? Accurate enough to
decide, for example, that the path from a multiplier, through its switch
box, via a double line, into the CLB to the left is slightly faster than
using the same double line to go to the CLB on the right?

Can any sort of assumptions be made in terms of ps per unit length from what
is seen in FPGA Editor? What's the cost (delay wise) of going through a PIP
FET?

Is this the wrong approach to making floorplanning decisions?

Thanks,

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"
 
I'm looking at an XC2V100-4FG456.
Click to expand...
Sorry, XC2V1000


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"
 
the FPGA editor is about as good as it gets for studying the device. Yes, it is
faithful to the device for the connections and relative locations of the
blocks. The router in FPGA editor will return timing for each node on a route
as well.

Martin Euredjian wrote:

In wanting to gain a greater understanding of routing options (particularly
as related to making floorplanning decisions) I find myself studing devices
in the FPGA Editor. One question that occured to me is: How accurate a
representation of the actual device layout does this tool provide? Example:

I'm looking at an XC2V100-4FG456. I see that all embedded multipliers have
the I/O on the left side only. Obviously all PIP's are on that side as
well. And there are four switch boxes that would seem to be the best place
to connect in/out of the multipler. These switch boxes, in turn, would be
the way to access the CLB's to the immediate left and right(through their
own switch boxes). Double interconnect lines seem to be the best possible
path.

Are these accurate representations of the geometry? Accurate enough to
decide, for example, that the path from a multiplier, through its switch
box, via a double line, into the CLB to the left is slightly faster than
using the same double line to go to the CLB on the right?

Can any sort of assumptions be made in terms of ps per unit length from what
is seen in FPGA Editor? What's the cost (delay wise) of going through a PIP
FET?

Is this the wrong approach to making floorplanning decisions?

Thanks,

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"
Click to expand...
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
 
Cannot answer your question, but thought I would bring to your attention
Xilinx XAPP636, "Optimal Pipelining of I/O Ports of the Virtex-II
Multiplier", in case you have not seen it.


"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:654hb.12932$ln2.10690@newssvr25.news.prodigy.com...
In wanting to gain a greater understanding of routing options
(particularly
as related to making floorplanning decisions) I find myself studing
devices
in the FPGA Editor. One question that occured to me is: How accurate a
representation of the actual device layout does this tool provide?
Example:

I'm looking at an XC2V100-4FG456. I see that all embedded multipliers
have
the I/O on the left side only. Obviously all PIP's are on that side as
well. And there are four switch boxes that would seem to be the best
place
to connect in/out of the multipler. These switch boxes, in turn, would be
the way to access the CLB's to the immediate left and right(through their
own switch boxes). Double interconnect lines seem to be the best possible
path.

Are these accurate representations of the geometry? Accurate enough to
decide, for example, that the path from a multiplier, through its switch
box, via a double line, into the CLB to the left is slightly faster than
using the same double line to go to the CLB on the right?

Can any sort of assumptions be made in terms of ps per unit length from
what
is seen in FPGA Editor? What's the cost (delay wise) of going through a
PIP
FET?

Is this the wrong approach to making floorplanning decisions?

Thanks,

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"
Click to expand...
 
"Barry Brown" <barry_brown@agilent.com> wrote in message
news:1065716279.409531@cswreg.cos.agilent.com...
Cannot answer your question, but thought I would bring to your attention
Xilinx XAPP636, "Optimal Pipelining of I/O Ports of the Virtex-II
Multiplier", in case you have not seen it.
Click to expand...
Yes, I have, thanks. I show that I downloaded it back in December '02.
Re-studied it a few days ago.


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"
 
FWIW, you need to put those registers in those spots around the multipliers in
order to achieve the data sheet max performance.

Martin Euredjian wrote:

"Barry Brown" <barry_brown@agilent.com> wrote in message
news:1065716279.409531@cswreg.cos.agilent.com...
Cannot answer your question, but thought I would bring to your attention
Xilinx XAPP636, "Optimal Pipelining of I/O Ports of the Virtex-II
Multiplier", in case you have not seen it.

Yes, I have, thanks. I show that I downloaded it back in December '02.
Re-studied it a few days ago.

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"
Click to expand...
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
 
"Ray Andraka" wrote:

FWIW, you need to put those registers in those spots around the
multipliers in
order to achieve the data sheet max performance.
Click to expand...
Right. I experimented with the XAPP636 placement and studied the routing in
and out of the multiplier with FPGA Editor. Makes sense. Can't see a
faster way to lay it out.

Funny enough, if you let the tools do a layout they will be exceedingly
happy to put FF's so far away from multipliers that a monkey with a dart
might be able to do better. This, I don't really understand.


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"
 
The tools do the same thing with pipeline registers added to BRAMs. They don't
seem to do very well with placement of and around the multipliers and BRAMs.

Martin Euredjian wrote:

"Ray Andraka" wrote:

FWIW, you need to put those registers in those spots around the
multipliers in
order to achieve the data sheet max performance.

Right. I experimented with the XAPP636 placement and studied the routing in
and out of the multiplier with FPGA Editor. Makes sense. Can't see a
faster way to lay it out.

Funny enough, if you let the tools do a layout they will be exceedingly
happy to put FF's so far away from multipliers that a monkey with a dart
might be able to do better. This, I don't really understand.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"
Click to expand...
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top