floating point synthesis on Xilinx FPGAs using ISE Webpack

[vicash]

Hi

I have been researching floating and/or fixed point support for Xilinx FPGAs that can be synthesized using the ISE Webpack toolkit. After foolishly trying to synthesize the "real" type and then researching various options I came across the following links:

http://www.eda-stds.org/fphdl/

http://www.vhdl.org/fphdl/vhdl.html

Now, I am a little confused as to how to go about using these sources. They mention using the IEEE_proposed library.

Q. Does that mean that Xilinx ISE will provide the IEEE_proposed library ?

Q. If not, do I have to compile this library myself using the provided source code for fixed and floating point math ?

Q. Has anyone successfully used this code and/or synthesized floating point on a Xilinx FPGA using ISE Webpack ?

Any help will be appreciated.

Thanks
vicash

 

[glen herrmannsfeldt]

vicash <walburn@gmail.com> wrote:

I have been researching floating and/or fixed point support
for Xilinx FPGAs that can be synthesized using the ISE Webpack
toolkit. After foolishly trying to synthesize the "real" type
and then researching various options I came across the
following links:

http://www.eda-stds.org/fphdl/

http://www.vhdl.org/fphdl/vhdl.html

Now, I am a little confused as to how to go about using
these sources. They mention using the IEEE_proposed library.

What are you actually trying to build? That makes a big difference
in how you do it.

In the usual case, one wants to accelerate some algorithm, which
usually means a pipeline that can process some data with very
high throughput. That pretty much means pipelining the floating
point operation if you want floating point.

Floating point takes a lot more CLBs than fixed point, especially
the floating point adder/subtracter.

-- glen

 

[mnentwig]

Hi,

you mentioned "floating point or fixed point". Don't know if this is of an
use, but if you can reasonably write the algorithm in fixed point, it ma
be the better choice. It's' easier for some problems than for others. And
it takes some time to get used to it.

Up to 18x18 bit (typically), you get one multiplication per hardwar
multiplier per clock cycle.
If possible, formulate your algorithm as a pipelined data path in 18 bit
and even a relatively small FPGA can do a serious amount of work.

Typical fixed point code could look like this
acc <= ((acc * xLSB + $signed(1 << 12)) >>> 13) + c2;

where "xLSB" has 12 fractional bits (right side of the decimal point).
Adding "1 << 12" and arithmetic (signed) right shift by 13 rounds at 0.
and restores the decimal point.
For high clock speed (~50+ MHz), it may need pipelining.
Also, saturation should be placed strategically throughout the code t
prevent that overflow wraps.

I've got a complete example for (simple) fixed point DSP RTL here:
http://www.dsprelated.com/showarticle/594.php


---------------------------------------
Posted through http://www.FPGARelated.com

 

[Thorsten Kiefer]

Am Freitag, 1. August 2014 18:06:30 UTC+2 schrieb vicash:

Hi



I have been researching floating and/or fixed point support for Xilinx FPGAs that can be synthesized using the ISE Webpack toolkit. After foolishly trying to synthesize the "real" type and then researching various options I came across the following links:



http://www.eda-stds.org/fphdl/



http://www.vhdl.org/fphdl/vhdl.html



Now, I am a little confused as to how to go about using these sources. They mention using the IEEE_proposed library.



Q. Does that mean that Xilinx ISE will provide the IEEE_proposed library ?



Q. If not, do I have to compile this library myself using the provided source code for fixed and floating point math ?



Q. Has anyone successfully used this code and/or synthesized floating point on a Xilinx FPGA using ISE Webpack ?



Any help will be appreciated.



Thanks

vicash

Did you try out Xilinx's floating point IP-Cores ?

Regards
Thorsten