floating point adder and multiplier

[mmt1]

Hi all
I'm doing an image processing project, in which I have to design a
floating point adder and multiplexer. There are 10 bits for mantissa, 6
bits for exponent and 1 bit for sign. So we have some 17 bit floating
point numbers that must add or multiplied by together.
First I write its verilog code, and then I want to design it in ASIC. I
look for a number of ready verilog codes which do the same operate. I
want to use them as the model. Can anyone help me? Thanks a lot before.
Regards,

 

[Amal]

Although this is not in Verilog, you can use the upcoming VHDL-200x-FT
package IEEE.Float_Pkg to do this. Or you can do your own modeling in
Verilog based on this. Take a look at the following for more
information.

http://www.eda.org/vhdl-200x/vhdl-200x-ft
http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/files.html

-- Amal