Flicker noise tutorial...

[Joe Gwinn]

While S.E.D. does not usually design ultra low noise oscillators, I
suspect that the discussions of the various physical and electronics
effects needing to be understood and addressed would be interesting in
its own right. This is a free download.

..<https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9286468>

This was cited in time-nuts Digest, Vol 227, Issue 8 (08 Mar 2023).

Joe Gwinn

 

[Phil Hobbs]

On 2023-03-09 16:48, Joe Gwinn wrote:

While S.E.D. does not usually design ultra low noise oscillators, I
suspect that the discussions of the various physical and electronics
effects needing to be understood and addressed would be interesting in
its own right. This is a free download.

.<https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9286468

This was cited in time-nuts Digest, Vol 227, Issue 8 (08 Mar 2023).

Joe Gwinn

Interesting paper, thanks. I haven\'t been keeping up with RF CMOS
design for the last dozen years or more, since I lost touch with most of
my IBM Watson colleagues, so this is a nudge in the right direction.

Focusing on the asymmetry of the waveforms as the point of entry for
flicker noise upconversion sounds about right, once you\'ve got rid of
the FET tail current source and the varactors.

To upconvert low-frequency stuff, you need to have a mechanism for the
phase shifting effect of slow current changes not to cancel out on
alternate half-cycles, so waveform asymmetry is pretty well it.

FET switches really only have Johnson noise, so switching resistors in
and out to compensate for process, voltage, and temperature (PVT) shifts
is a cute idea.

I\'m less clear on why replacing the varactors with a bunch of caps and
switches is a win, but apparently it is, at least from a flicker noise
POV. Sure seems like a lot of gingerbread to hang on a 28 GHz tank circuit!

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Kevin Aylward]

\"Joe Gwinn\" wrote in message
news:amkk0i1t7jl94060ctufaojti69kmsurda@4ax.com...

While S.E.D. does not usually design ultra low noise oscillators, I
suspect that the discussions of the various physical and electronics
effects needing to be understood and addressed would be interesting in
its own right. This is a free download.

..<https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9286468>

This was cited in time-nuts Digest, Vol 227, Issue 8 (08 Mar 2023).

Joe Gwinn

Ahmmmmmmm..... and...... er.....well.... I know a tad about low phase noise
oscillators.....

The H-L \"theory\" is proven false. It simply doesn\'t work. Its assumptions
are simply wrong.

I have a full detailed account as to why here:

https://www.kevinaylward.co.uk/ee/phasenoise/phasenoise.html

Fundamentally, H-L fails, intrinsically, whenever there is a nonlinear
capacitor, which is, essentially, in all circuits.

The key paper by Alper Demir, Bell Labs, showing why the H-L technique is
toilet paper is in the references:

https://www.kevinaylward.co.uk/ee/phasenoise/A-Demir.pdf

\"… The right-hand-side (RHS) of the differential equation (13) for the phase
error is nonlinear. Thus, one can not use superposition to calculate the
phase error due to several perturbations, i.e., one can not calculate the
phase errors due to two perturbations separately and then sum them up to
obtain the phase error due to the two perturbations applied at the same
time.\"

and

1 A. Demi1, with reference to the HL model, mathematically
proves and states:

1.1 Is the orthogonal decomposition valid in general?

1.2 Even if it is not strictly valid, can it provide
approximately correct results and intuition for practical oscillator
designs?

1.3 We show that the answer to both questions is negative.

1.4 ...it can predict results off by as much as 50 dBc/Hz.

The key statements being from:

https://www.kevinaylward.co.uk/ee/phasenoise/LTV.xht

This paper explains in more simpler terms exactly why symmetrical circuits
can generate up conversion and why time variance is not an explanation for
up conversion.

The technique Demir development to correctly calculate phase noise was
incorporated into the Mentor Graphics design suits when they purchased
Berkely Design

Its simply astounding that a paper published in 2021 in the IEEE is
presenting such erroneous twaddle.

..and... for the removal of doubt.... I have been an TCXO/OCXO oscillator
ASIC designer for a major player in that space for 15 years...

Kevin Aylward

http://www.anasoft.co.uk/ SuperSpice Simulation
http://www.kevinaylward.co.uk/ee/index.html - Electronics
https://www.kevinaylward.co.uk/gr/index.html - General Relativity

 

[Kevin Aylward]

\"Phil Hobbs\" wrote in message
news:25051584-77a4-aa8b-0d5f-3eeb981aae38@electrooptical.net...

On 2023-03-09 16:48, Joe Gwinn wrote:

While S.E.D. does not usually design ultra low noise oscillators, I
suspect that the discussions of the various physical and electronics
effects needing to be understood and addressed would be interesting in
its own right. This is a free download.

.<https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9286468

This was cited in time-nuts Digest, Vol 227, Issue 8 (08 Mar 2023).

Joe Gwinn


Interesting paper, thanks. I haven\'t been keeping up with RF CMOS design
for the last dozen years or more, since I lost touch with most of my IBM
Watson colleagues, so this is a nudge in the right direction.

Focusing on the asymmetry of the waveforms as the point of entry for
flicker noise upconversion sounds about right, once you\'ve got rid of the
FET tail current source and the varactors.

To upconvert low-frequency stuff, you need to have a mechanism for the
phase shifting effect of slow current changes not to cancel out on
alternate half-cycles, so waveform asymmetry is pretty well it.

All up-converion requires is a non-linear capacitor. It don\'t matter if the
waveform is symmetrical, explained here:

https://www.kevinaylward.co.uk/ee/phasenoise/LTV.xht

FET switches really only have Johnson noise, so switching resistors in and
out to compensate for process, voltage, and temperature (PVT) shifts is a
cute idea.

CMOS switches have significant 1/f noise, even when notionally having no
\"dc\" in them. Its a major problem in the design of LN oscillators.

The current in them due to the AC signal constitutes an effective dc bias
current that generates the 1/f noise

For example, the Cadence Spectre simulator models this very accurately.

I\'m less clear on why replacing the varactors with a bunch of caps and
switches is a win, but apparently it is, at least from a flicker noise POV.
Sure seems like a lot of gingerbread to hang on a 28 GHz tank circuit!

Cheers

Phil Hobbs

I wont repeat what posted as a reply to the original post, however...

Using selectable fixed caps instead of having wider varactor control is
easily explained.

All noise, whether 1/f or flatband applied to a varactor directly causes
frequency modulation. Its a disaster.

If all tuning is done by the varactor, than one needs a wide pull range,
that is a large K gain modulation constant of the VCO

If the tuning is staggered by fixed capacitors than the modulation constant
can be made less, by design, thus the frequency modulation is minimised.

Kevin Aylward

https://www.kevinaylward.co.uk/gr/index.html - General Relativity
http://www.anasoft.co.uk/ SuperSpice Simulation
http://www.kevinaylward.co.uk/ee/index.html - Electronics

 

[Jan Panteltje]

On a sunny day (Sun, 12 Mar 2023 13:06:00 -0000) it happened \"Kevin Aylward\"
<kevinRemoveandReplaceATkevinaylward.co.uk> wrote in
<bB6dnVuxevdyUJD5nZ2dnZeNn_dh4p2d@giganews.com>:

\"Joe Gwinn\" wrote in message
news:amkk0i1t7jl94060ctufaojti69kmsurda@4ax.com...

While S.E.D. does not usually design ultra low noise oscillators, I
suspect that the discussions of the various physical and electronics
effects needing to be understood and addressed would be interesting in
its own right. This is a free download.

.<https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9286468

This was cited in time-nuts Digest, Vol 227, Issue 8 (08 Mar 2023).

Joe Gwinn

Ahmmmmmmm..... and...... er.....well.... I know a tad about low phase noise
oscillators.....

The H-L \"theory\" is proven false. It simply doesn\'t work. Its assumptions
are simply wrong.

I have a full detailed account as to why here:

https://www.kevinaylward.co.uk/ee/phasenoise/phasenoise.html

Fundamentally, H-L fails, intrinsically, whenever there is a nonlinear
capacitor, which is, essentially, in all circuits.

The key paper by Alper Demir, Bell Labs, showing why the H-L technique is
toilet paper is in the references:

https://www.kevinaylward.co.uk/ee/phasenoise/A-Demir.pdf

\"… The right-hand-side (RHS) of the differential equation (13) for the phase
error is nonlinear. Thus, one can not use superposition to calculate the
phase error due to several perturbations, i.e., one can not calculate the
phase errors due to two perturbations separately and then sum them up to
obtain the phase error due to the two perturbations applied at the same
time.\"

and

1 A. Demi1, with reference to the HL model, mathematically
proves and states:

1.1 Is the orthogonal decomposition valid in general?

1.2 Even if it is not strictly valid, can it provide
approximately correct results and intuition for practical oscillator
designs?

1.3 We show that the answer to both questions is negative.

1.4 ...it can predict results off by as much as 50 dBc/Hz.

The key statements being from:

https://www.kevinaylward.co.uk/ee/phasenoise/LTV.xht

This paper explains in more simpler terms exactly why symmetrical circuits
can generate up conversion and why time variance is not an explanation for
up conversion.

The technique Demir development to correctly calculate phase noise was
incorporated into the Mentor Graphics design suits when they purchased
Berkely Design

Its simply astounding that a paper published in 2021 in the IEEE is
presenting such erroneous twaddle.

.and... for the removal of doubt.... I have been an TCXO/OCXO oscillator
ASIC designer for a major player in that space for 15 years...

Kevin Aylward

http://www.anasoft.co.uk/ SuperSpice Simulation
http://www.kevinaylward.co.uk/ee/index.html - Electronics
https://www.kevinaylward.co.uk/gr/index.html - General Relativity

Thank you,
I did download that IEEE paper, had a look and some internal alarm went off
said: crap
Have now deleted it.

 

[John Larkin]

On Sun, 12 Mar 2023 13:30:15 -0000, \"Kevin Aylward\"
<kevinRemoveandReplaceATkevinaylward.co.uk> wrote:

\"Phil Hobbs\" wrote in message
news:25051584-77a4-aa8b-0d5f-3eeb981aae38@electrooptical.net...

On 2023-03-09 16:48, Joe Gwinn wrote:

While S.E.D. does not usually design ultra low noise oscillators, I
suspect that the discussions of the various physical and electronics
effects needing to be understood and addressed would be interesting in
its own right. This is a free download.

.<https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9286468

This was cited in time-nuts Digest, Vol 227, Issue 8 (08 Mar 2023).

Joe Gwinn


Interesting paper, thanks. I haven\'t been keeping up with RF CMOS design
for the last dozen years or more, since I lost touch with most of my IBM
Watson colleagues, so this is a nudge in the right direction.

Focusing on the asymmetry of the waveforms as the point of entry for
flicker noise upconversion sounds about right, once you\'ve got rid of the
FET tail current source and the varactors.

To upconvert low-frequency stuff, you need to have a mechanism for the
phase shifting effect of slow current changes not to cancel out on
alternate half-cycles, so waveform asymmetry is pretty well it.

All up-converion requires is a non-linear capacitor. It don\'t matter if the
waveform is symmetrical, explained here:

https://www.kevinaylward.co.uk/ee/phasenoise/LTV.xht

FET switches really only have Johnson noise, so switching resistors in and
out to compensate for process, voltage, and temperature (PVT) shifts is a
cute idea.

CMOS switches have significant 1/f noise, even when notionally having no
\"dc\" in them. Its a major problem in the design of LN oscillators.

The current in them due to the AC signal constitutes an effective dc bias
current that generates the 1/f noise

For example, the Cadence Spectre simulator models this very accurately.

I\'m less clear on why replacing the varactors with a bunch of caps and
switches is a win, but apparently it is, at least from a flicker noise POV.
Sure seems like a lot of gingerbread to hang on a 28 GHz tank circuit!

Cheers

Phil Hobbs

I wont repeat what posted as a reply to the original post, however...

Using selectable fixed caps instead of having wider varactor control is
easily explained.

All noise, whether 1/f or flatband applied to a varactor directly causes
frequency modulation. Its a disaster.

If all tuning is done by the varactor, than one needs a wide pull range,
that is a large K gain modulation constant of the VCO

If the tuning is staggered by fixed capacitors than the modulation constant
can be made less, by design, thus the frequency modulation is minimised.

Kevin Aylward

https://www.kevinaylward.co.uk/gr/index.html - General Relativity
http://www.anasoft.co.uk/ SuperSpice Simulation
http://www.kevinaylward.co.uk/ee/index.html - Electronics

I make triggered LC oscillators as the timebase for delay generators.
I want my varicap to have a narrow pull range, just enough to stay
phaselocked over temperature, like +- a few hundred PPM, to keep phase
noise down. Varicaps are horrible capacitors!

So at powerup I center my oscillator with a digital cap.

PEREGRINE PE64907MLAA-Z

seems to work great. I haven\'t investigated what might be the FM
contribution from any non-ideal behavior of the digital cap.

 

[Kevin Aylward]

\"John Larkin\" wrote in message
news:upsr0i17ukq02jfpvm53as5d4357f338uv@4ax.com...

On Sun, 12 Mar 2023 13:30:15 -0000, \"Kevin Aylward\"
<kevinRemoveandReplaceATkevinaylward.co.uk> wrote:

\"Phil Hobbs\" wrote in message
news:25051584-77a4-aa8b-0d5f-3eeb981aae38@electrooptical.net...

On 2023-03-09 16:48, Joe Gwinn wrote:

While S.E.D. does not usually design ultra low noise oscillators, I
suspect that the discussions of the various physical and electronics
effects needing to be understood and addressed would be interesting in
its own right. This is a free download.

.<https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9286468

This was cited in time-nuts Digest, Vol 227, Issue 8 (08 Mar 2023).

Joe Gwinn


Interesting paper, thanks. I haven\'t been keeping up with RF CMOS design
for the last dozen years or more, since I lost touch with most of my IBM
Watson colleagues, so this is a nudge in the right direction.

Focusing on the asymmetry of the waveforms as the point of entry for
flicker noise upconversion sounds about right, once you\'ve got rid of the
FET tail current source and the varactors.

To upconvert low-frequency stuff, you need to have a mechanism for the
phase shifting effect of slow current changes not to cancel out on
alternate half-cycles, so waveform asymmetry is pretty well it.

All up-converion requires is a non-linear capacitor. It don\'t matter if the
waveform is symmetrical, explained here:

https://www.kevinaylward.co.uk/ee/phasenoise/LTV.xht

FET switches really only have Johnson noise, so switching resistors in and
out to compensate for process, voltage, and temperature (PVT) shifts is a
cute idea.

CMOS switches have significant 1/f noise, even when notionally having no
\"dc\" in them. Its a major problem in the design of LN oscillators.

The current in them due to the AC signal constitutes an effective dc bias
current that generates the 1/f noise

For example, the Cadence Spectre simulator models this very accurately.

I\'m less clear on why replacing the varactors with a bunch of caps and
switches is a win, but apparently it is, at least from a flicker noise
POV.
Sure seems like a lot of gingerbread to hang on a 28 GHz tank circuit!

Cheers

Phil Hobbs

I wont repeat what posted as a reply to the original post, however...

Using selectable fixed caps instead of having wider varactor control is
easily explained.

All noise, whether 1/f or flatband applied to a varactor directly causes
frequency modulation. Its a disaster.

If all tuning is done by the varactor, than one needs a wide pull range,
that is a large K gain modulation constant of the VCO

If the tuning is staggered by fixed capacitors than the modulation
constant
can be made less, by design, thus the frequency modulation is minimised.

Kevin Aylward

I make triggered LC oscillators as the timebase for delay generators.
I want my varicap to have a narrow pull range, just enough to stay
phaselocked over temperature, like +- a few hundred PPM, to keep phase
noise down. Varicaps are horrible capacitors!

Yes.

I\'m using mosfet caps. Below 0V they crap out.

Fabs don\'t model them well. Current one from the Fab has the temp co with
the wrong sign. It don\'t work like one would naively expect from theory.

So at powerup I center my oscillator with a digital cap.

PEREGRINE PE64907MLAA-Z

seems to work great. I haven\'t investigated what might be the FM
contribution from any non-ideal behavior of the digital cap.

What I have discovered after running 10,000s of phase noise simulations and
comparing to physical measurements, is that it is simply impossible to
pencil and paper phase noise.

A divide by 2 gives a hump in the flatband. A divide by 3 gets lower
flatband phase noise than a divide by 4, sometimes.....

Its all darkness.....


https://www.kevinaylward.co.uk/gr/index.html - General Relativity
http://www.anasoft.co.uk/ SuperSpice Simulation
http://www.kevinaylward.co.uk/ee/index.html - Electronics

 

[Kevin Aylward]

\"Jan Panteltje\" wrote in message news:tuklsc$20dgi$1@solani.org...

On a sunny day (Sun, 12 Mar 2023 13:06:00 -0000) it happened \"Kevin Aylward\"
<kevinRemoveandReplaceATkevinaylward.co.uk> wrote in
<bB6dnVuxevdyUJD5nZ2dnZeNn_dh4p2d@giganews.com>:

\"Joe Gwinn\" wrote in message
news:amkk0i1t7jl94060ctufaojti69kmsurda@4ax.com...

While S.E.D. does not usually design ultra low noise oscillators, I
suspect that the discussions of the various physical and electronics
effects needing to be understood and addressed would be interesting in
its own right. This is a free download.

.<https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9286468

This was cited in time-nuts Digest, Vol 227, Issue 8 (08 Mar 2023).

Joe Gwinn

Ahmmmmmmm..... and...... er.....well.... I know a tad about low phase noise
oscillators.....

The H-L \"theory\" is proven false. It simply doesn\'t work. Its assumptions
are simply wrong.

I have a full detailed account as to why here:

https://www.kevinaylward.co.uk/ee/phasenoise/phasenoise.html

Fundamentally, H-L fails, intrinsically, whenever there is a nonlinear
capacitor, which is, essentially, in all circuits.

The key paper by Alper Demir, Bell Labs, showing why the H-L technique is
toilet paper is in the references:

https://www.kevinaylward.co.uk/ee/phasenoise/A-Demir.pdf

\"⤦ The right-hand-side (RHS) of the differential equation (13) for the
phase
error is nonlinear. Thus, one can not use superposition to calculate the
phase error due to several perturbations, i.e., one can not calculate the
phase errors due to two perturbations separately and then sum them up to
obtain the phase error due to the two perturbations applied at the same
time.\"

and

1 A. Demi1, with reference to the HL model, mathematically
proves and states:

1.1 Is the orthogonal decomposition valid in general?

1.2 Even if it is not strictly valid, can it provide
approximately correct results and intuition for practical oscillator
designs?

1.3 We show that the answer to both questions is
negative.

1.4 ...it can predict results off by as much as 50
dBc/Hz.

The key statements being from:

https://www.kevinaylward.co.uk/ee/phasenoise/LTV.xht

This paper explains in more simpler terms exactly why symmetrical circuits
can generate up conversion and why time variance is not an explanation for
up conversion.

The technique Demir development to correctly calculate phase noise was
incorporated into the Mentor Graphics design suits when they purchased
Berkely Design

Its simply astounding that a paper published in 2021 in the IEEE is
presenting such erroneous twaddle.

.and... for the removal of doubt.... I have been an TCXO/OCXO oscillator
ASIC designer for a major player in that space for 15 years...

Kevin Aylward

>Thank you,

Glad to help.....

I did download that IEEE paper, had a look and some internal alarm went off
said: crap
Have now deleted it.

I realised that H-L was wrong immediately with their claim that had on
having the same physical circuit but either inside a box or outside the box
one generated up conversion and one didn\'t.

Details here, near the bottom of the page.

https://www.kevinaylward.co.uk/ee/phasenoise/LTV.xht

The other immediate giveaway is that they used a drive of cos(wt) to get a
sin(wt)/wt response for phase. Sin(wt)/wt has a limit of 1 for x->0

However, there is no logical reason that the analysis couldn\'t have just
started with sin(wt) to get a cos(x)/x phase, which goes to infinity as x->0

Thus their fundamental formula for up conversion had to be false. They had
to cherry pick an input signal to get a non singular solution. It was
blatantly dishonest, imo.

I then did the search to discover the A. Dimer paper. I then run SuperSpice
simulations to see the effect of generating a phase error by hitting the
peak of the waveform.

I also ran a set of simulations in the expensive Cadence spectre to discover
what conditions actually generated up-converted PN.

https://www.kevinaylward.co.uk/ee/phasenoise/PhaseNoiseOscillators.xht

The correlation between the simulations and measurements is very good.

Everything ties up. H-L were just pissing in the wind.

Kevin Aylward

https://www.kevinaylward.co.uk/gr/index.html - General Relativity
http://www.anasoft.co.uk/ SuperSpice Simulation
http://www.kevinaylward.co.uk/ee/index.html - Electronics

 

[John Larkin]

On Sun, 12 Mar 2023 18:19:14 -0000, \"Kevin Aylward\"
<kevinRemoveandReplaceATkevinaylward.co.uk> wrote:

\"John Larkin\" wrote in message
news:upsr0i17ukq02jfpvm53as5d4357f338uv@4ax.com...

On Sun, 12 Mar 2023 13:30:15 -0000, \"Kevin Aylward\"
kevinRemoveandReplaceATkevinaylward.co.uk> wrote:




\"Phil Hobbs\" wrote in message
news:25051584-77a4-aa8b-0d5f-3eeb981aae38@electrooptical.net...

On 2023-03-09 16:48, Joe Gwinn wrote:

While S.E.D. does not usually design ultra low noise oscillators, I
suspect that the discussions of the various physical and electronics
effects needing to be understood and addressed would be interesting in
its own right. This is a free download.

.<https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9286468

This was cited in time-nuts Digest, Vol 227, Issue 8 (08 Mar 2023).

Joe Gwinn


Interesting paper, thanks. I haven\'t been keeping up with RF CMOS design
for the last dozen years or more, since I lost touch with most of my IBM
Watson colleagues, so this is a nudge in the right direction.

Focusing on the asymmetry of the waveforms as the point of entry for
flicker noise upconversion sounds about right, once you\'ve got rid of the
FET tail current source and the varactors.

To upconvert low-frequency stuff, you need to have a mechanism for the
phase shifting effect of slow current changes not to cancel out on
alternate half-cycles, so waveform asymmetry is pretty well it.

All up-converion requires is a non-linear capacitor. It don\'t matter if the
waveform is symmetrical, explained here:

https://www.kevinaylward.co.uk/ee/phasenoise/LTV.xht

FET switches really only have Johnson noise, so switching resistors in and
out to compensate for process, voltage, and temperature (PVT) shifts is a
cute idea.

CMOS switches have significant 1/f noise, even when notionally having no
\"dc\" in them. Its a major problem in the design of LN oscillators.

The current in them due to the AC signal constitutes an effective dc bias
current that generates the 1/f noise

For example, the Cadence Spectre simulator models this very accurately.

I\'m less clear on why replacing the varactors with a bunch of caps and
switches is a win, but apparently it is, at least from a flicker noise
POV.
Sure seems like a lot of gingerbread to hang on a 28 GHz tank circuit!

Cheers

Phil Hobbs

I wont repeat what posted as a reply to the original post, however...

Using selectable fixed caps instead of having wider varactor control is
easily explained.

All noise, whether 1/f or flatband applied to a varactor directly causes
frequency modulation. Its a disaster.

If all tuning is done by the varactor, than one needs a wide pull range,
that is a large K gain modulation constant of the VCO

If the tuning is staggered by fixed capacitors than the modulation
constant
can be made less, by design, thus the frequency modulation is minimised.

Kevin Aylward



I make triggered LC oscillators as the timebase for delay generators.
I want my varicap to have a narrow pull range, just enough to stay
phaselocked over temperature, like +- a few hundred PPM, to keep phase
noise down. Varicaps are horrible capacitors!

Yes.

I\'m using mosfet caps. Below 0V they crap out.

Fabs don\'t model them well. Current one from the Fab has the temp co with
the wrong sign. It don\'t work like one would naively expect from theory.

So at powerup I center my oscillator with a digital cap.

PEREGRINE PE64907MLAA-Z

seems to work great. I haven\'t investigated what might be the FM
contribution from any non-ideal behavior of the digital cap.

What I have discovered after running 10,000s of phase noise simulations and
comparing to physical measurements, is that it is simply impossible to
pencil and paper phase noise.

A divide by 2 gives a hump in the flatband. A divide by 3 gets lower
flatband phase noise than a divide by 4, sometimes.....

Its all darkness.....

Well, it\'s complex enough that I can justify not using theory. Spice,
guess, prototype.

The worst capacitor is the FR4 PC board. Good parts placement and
cutting holes in planes helps with that.

My triggerd oscillators have an inductor (that\'s a whole nother story)
and one good NPO cap, then a padded NTC cap, then the digital cap, and
finally the varicap. Labor intensive to prototype and test, especially
tempcos. The oscillators are phase-locked to an XO in under a
microsecond after startup, so low frequency phase noise is not an
issue.

https://www.dropbox.com/s/2uoeruouhcoz6al/Z482_Can.jpg?raw=1

https://www.dropbox.com/s/30c6aesh4tzjg56/Z496_Can.jpg?raw=1

I played with coaxial ceramic resonators, which should be much better
than LCs, but there were practical difficulties. I might try again.

 

[Joe Gwinn]

On Sun, 12 Mar 2023 18:15:01 -0000, \"Kevin Aylward\"
<kevinRemoveandReplaceATkevinaylward.co.uk> wrote:

\"Jan Panteltje\" wrote in message news:tuklsc$20dgi$1@solani.org...

On a sunny day (Sun, 12 Mar 2023 13:06:00 -0000) it happened \"Kevin Aylward\"
kevinRemoveandReplaceATkevinaylward.co.uk> wrote in
bB6dnVuxevdyUJD5nZ2dnZeNn_dh4p2d@giganews.com>:

\"Joe Gwinn\" wrote in message
news:amkk0i1t7jl94060ctufaojti69kmsurda@4ax.com...

While S.E.D. does not usually design ultra low noise oscillators, I
suspect that the discussions of the various physical and electronics
effects needing to be understood and addressed would be interesting in
its own right. This is a free download.

.<https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9286468

This was cited in time-nuts Digest, Vol 227, Issue 8 (08 Mar 2023).

Joe Gwinn

Ahmmmmmmm..... and...... er.....well.... I know a tad about low phase noise
oscillators.....

The H-L \"theory\" is proven false. It simply doesn\'t work. Its assumptions
are simply wrong.

I have a full detailed account as to why here:

https://www.kevinaylward.co.uk/ee/phasenoise/phasenoise.html

Fundamentally, H-L fails, intrinsically, whenever there is a nonlinear
capacitor, which is, essentially, in all circuits.

The key paper by Alper Demir, Bell Labs, showing why the H-L technique is
toilet paper is in the references:

https://www.kevinaylward.co.uk/ee/phasenoise/A-Demir.pdf

\"The right-hand-side (RHS) of the differential equation (13) for the
phase
error is nonlinear. Thus, one can not use superposition to calculate the
phase error due to several perturbations, i.e., one can not calculate the
phase errors due to two perturbations separately and then sum them up to
obtain the phase error due to the two perturbations applied at the same
time.\"

and
[snip]

The key statements being from:

https://www.kevinaylward.co.uk/ee/phasenoise/LTV.xht

This paper explains in more simpler terms exactly why symmetrical circuits
can generate up conversion and why time variance is not an explanation for
up conversion.
[snip]


Thank you,

Glad to help.....

I did download that IEEE paper, had a look and some internal alarm went off
said: crap
Have now deleted it.

I realised that H-L was wrong immediately with their claim that had on
having the same physical circuit but either inside a box or outside the box
one generated up conversion and one didn\'t.

Details here, near the bottom of the page.

https://www.kevinaylward.co.uk/ee/phasenoise/LTV.xht

The other immediate giveaway is that they used a drive of cos(wt) to get a
sin(wt)/wt response for phase. Sin(wt)/wt has a limit of 1 for x->0

However, there is no logical reason that the analysis couldn\'t have just
started with sin(wt) to get a cos(x)/x phase, which goes to infinity as x->0

Thus their fundamental formula for up conversion had to be false. They had
to cherry pick an input signal to get a non singular solution. It was
blatantly dishonest, imo.

I then did the search to discover the A. Dimer paper. I then run SuperSpice
simulations to see the effect of generating a phase error by hitting the
peak of the waveform.

I also ran a set of simulations in the expensive Cadence spectre to discover
what conditions actually generated up-converted PN.

https://www.kevinaylward.co.uk/ee/phasenoise/PhaseNoiseOscillators.xht

The correlation between the simulations and measurements is very good.

Everything ties up. H-L were just pissing in the wind.

In your paper, you use Volterra Series (VSs) to solve the problem, and
it works quite well. The problem is that VSs are far too complicated
and difficult to use, yielding answers that are far too opaque for
intuition to be gained. (I know a person who used VSs to design
frequency multiplier circuits, and he could explain essentially
nothing. But his multipliers worked quite well.)

So why do people keep on using H-L? Basically for lack of a better
approach, people use H-L as a useful approximation and press on.

I also worry that VSs are too powerful, preventing us from seeing
simpler but perfectly adequate approaches.

So the question is if there is a better method than H-L, but far
simpler and more intuitive than VSs?

Demir uses he perturbed differential equations with limit cycles,
which is certainly simpler than VSs, but people keep on using H-L, so
even Demir may be too complicated for the purpose.

In the time world, flicker noise is often mathematically modeled as
the sum of terms of the form Kn*(f^-n), where n = {0,1,2,3,4}. This
works very well, but blows up at f=0, the carrier. No infinities are
encountered in practice, because the carrier line shape is a mix of
Gaussian and Lorentzian, with finite total power.

Joe Gwinn

 

[Kevin Aylward]

\"Joe Gwinn\" wrote in message
news:09641i1knalos772l9ru4he9rtt39nq0k9@4ax.com...

Thank you,

Glad to help.....

I did download that IEEE paper, had a look and some internal alarm went
off
said: crap
Have now deleted it.

I realised that H-L was wrong immediately with their claim that had on
having the same physical circuit but either inside a box or outside the
box
one generated up conversion and one didn\'t.

Details here, near the bottom of the page.

https://www.kevinaylward.co.uk/ee/phasenoise/LTV.xht

The other immediate giveaway is that they used a drive of cos(wt) to get a
sin(wt)/wt response for phase. Sin(wt)/wt has a limit of 1 for x->0

However, there is no logical reason that the analysis couldn\'t have just
started with sin(wt) to get a cos(x)/x phase, which goes to infinity as
x->0

Thus their fundamental formula for up conversion had to be false. They had
to cherry pick an input signal to get a non singular solution. It was
blatantly dishonest, imo.

I then did the search to discover the A. Dimer paper. I then run
SuperSpice
simulations to see the effect of generating a phase error by hitting the
peak of the waveform.

I also ran a set of simulations in the expensive Cadence spectre to
discover
what conditions actually generated up-converted PN.

https://www.kevinaylward.co.uk/ee/phasenoise/PhaseNoiseOscillators.xht

The correlation between the simulations and measurements is very good.

Everything ties up. H-L were just pissing in the wind.

In your paper, you use Volterra Series (VSs) to solve the problem, and
it works quite well. The problem is that VSs are far too complicated
and difficult to use, yielding answers that are far too opaque for
intuition to be gained. (I know a person who used VSs to design
frequency multiplier circuits, and he could explain essentially
nothing. But his multipliers worked quite well.)

I did some sums simply to illustrate the principle of the issue

There was no intention that such an approach was an attempt to solve any
practical phase nose problems.

Real circuits are way too complicated to actually use that approach.

So why do people keep on using H-L? Basically for lack of a better
approach, people use H-L as a useful approximation and press on.

They haven\'t cottoned on the fact that the only realistic way to design low
phase noise circuits is to use simulation.

A major problem is that to have papers published, one can\'t just go, I multi
swept 10 components and this combination gave the best result.

One has to hand wave mathematical twaddle to appear to know what one is
talking about. Its all a scam.

I also worry that VSs are too powerful, preventing us from seeing
simpler but perfectly adequate approaches.

There are no viable approaches other than using expensive simulation
programs.

So the question is if there is a better method than H-L, but far
simpler and more intuitive than VSs?

See above

Demir uses he perturbed differential equations with limit cycles,
which is certainly simpler than VSs, but people keep on using H-L, so
even Demir may be too complicated for the purpose.

The Demir approach is strictly a computer method.

In the time world, flicker noise is often mathematically modeled as
the sum of terms of the form Kn*(f^-n), where n = {0,1,2,3,4}. This
works very well, but blows up at f=0, the carrier. No infinities are
encountered in practice, because the carrier line shape is a mix of
Gaussian and Lorentzian, with finite total power.

There is simply no point in any attempt to design low phase noise circuits
by paper and pencil.

Realistically, few professional analog ASIC design engineers understand how
simulation tools solve the circuits they \"design\".

Fortunately, most designs are copied, then copied, then copied.... from the
few experts that might...

The world has moved on. When H-L was being developed, it was around 1995.
Phase Noise simulations tools were not widely available then.
If they were, they would have discovered their errors.

To solve even a trivial circuit analytically involves higher level functions
e.g.

https://www.kevinaylward.co.uk/ee/widlarlambert/widlarlambert.xht

Its just not worth the effort when simulation just does it all in the wash.

Modern design, for trillions of production ASICs, is performed entirely in
the virtual world.

One can only gain an in-depth understanding of complicated circuits by
simulation.

The tools spit out the relative contribution to phase nose from all
components at any frequency.

One uses a manual Darwinian Algorithm to home in to an optimum. Its the
random generation that makes one seem clever.

I typically run 100,000s of simulations a year in designing ASICs, running a
1000s times faster than in 2000, which is 1000 faster than the early 80s

Kevin Aylward

https://www.kevinaylward.co.uk/gr/index.html - General Relativity
http://www.anasoft.co.uk/ SuperSpice Simulation
http://www.kevinaylward.co.uk/ee/index.html - Electronics

 

[Joe Gwinn]

On Fri, 17 Mar 2023 18:51:36 -0000, \"Kevin Aylward\"
<kevinRemoveandReplaceATkevinaylward.co.uk> wrote:

\"Joe Gwinn\" wrote in message
news:09641i1knalos772l9ru4he9rtt39nq0k9@4ax.com...


Thank you,

Glad to help.....

I did download that IEEE paper, had a look and some internal alarm went
off
said: crap
Have now deleted it.

I realised that H-L was wrong immediately with their claim that had on
having the same physical circuit but either inside a box or outside the
box
one generated up conversion and one didn\'t.

Details here, near the bottom of the page.

https://www.kevinaylward.co.uk/ee/phasenoise/LTV.xht

The other immediate giveaway is that they used a drive of cos(wt) to get a
sin(wt)/wt response for phase. Sin(wt)/wt has a limit of 1 for x->0

However, there is no logical reason that the analysis couldn\'t have just
started with sin(wt) to get a cos(x)/x phase, which goes to infinity as
x->0

Thus their fundamental formula for up conversion had to be false. They had
to cherry pick an input signal to get a non singular solution. It was
blatantly dishonest, imo.

I then did the search to discover the A. Dimer paper. I then run
SuperSpice
simulations to see the effect of generating a phase error by hitting the
peak of the waveform.

I also ran a set of simulations in the expensive Cadence spectre to
discover
what conditions actually generated up-converted PN.

https://www.kevinaylward.co.uk/ee/phasenoise/PhaseNoiseOscillators.xht

The correlation between the simulations and measurements is very good.

Everything ties up. H-L were just pissing in the wind.

In your paper, you use Volterra Series (VSs) to solve the problem, and
it works quite well. The problem is that VSs are far too complicated
and difficult to use, yielding answers that are far too opaque for
intuition to be gained. (I know a person who used VSs to design
frequency multiplier circuits, and he could explain essentially
nothing. But his multipliers worked quite well.)

I did some sums simply to illustrate the principle of the issue

There was no intention that such an approach was an attempt to solve any
practical phase noise problems.

But many people in the time world are doing just that.

Real circuits are way too complicated to actually use that approach.

So why do people keep on using H-L? Basically for lack of a better
approach, people use H-L as a useful approximation and press on.

They haven\'t cottoned on the fact that the only realistic way to design low
phase noise circuits is to use simulation.

A major problem is that to have papers published, one can\'t just go, I multi
swept 10 components and this combination gave the best result.

One has to hand wave mathematical twaddle to appear to know what one is
talking about. Its all a scam.

In the time world, one can definitely publish circuit optimization
result papers, not just math papers. Both are useful.

I also worry that VSs are too powerful, preventing us from seeing
simpler but perfectly adequate approaches.

There are no viable approaches other than using expensive simulation
programs.

So the question is if there is a better method than H-L, but far
simpler and more intuitive than VSs?

See above

Demir uses he perturbed differential equations with limit cycles,
which is certainly simpler than VSs, but people keep on using H-L, so
even Demir may be too complicated for the purpose.

The Demir approach is strictly a computer method.

In practice, yes. Which is why it is little used in the time world,
except for detailed circuit design I assume. What is then published
in the form of a product.

In the time world, flicker noise is often mathematically modeled as
the sum of terms of the form Kn*(f^-n), where n = {0,1,2,3,4}. This
works very well, but blows up at f=0, the carrier. No infinities are
encountered in practice, because the carrier line shape is a mix of
Gaussian and Lorentzian, with finite total power.


There is simply no point in any attempt to design low phase noise circuits
by paper and pencil.

Agree. But that was not the suggestion. The time folk are very
mathematical and know physics, and they are always looking for a
better approximation, so they can explore immense architecture spaces,
far too large to explore adequately with simulation.

Realistically, few professional analog ASIC design engineers understand how
simulation tools solve the circuits they \"design\".

I don\'t know about that. The ASIC designers I know very much use
simulation, and have the same kinds of tools as you mention.

Fortunately, most designs are copied, then copied, then copied.... from the
few experts that might...

The world has moved on. When H-L was being developed, it was around 1995.
Phase Noise simulations tools were not widely available then.
If they were, they would have discovered their errors.

H-L were looking for a mathematically tractable approximation. I
agree that they likely didn\'t realize that their equation was so
easily criticized, but most likely the only change would have been to
admit that and claim that while their model was not exact, it was
nonetheless useful.

War story: Some years ago, I was trying to figure out a
signal-processing related problem, how deep the valley between two
Lorentzian or Gaussian peaks was as a function of separation and
difference in peak amplitude, and a few other things. People had been
solving this using Monte-Carlo methods, because the math was far too
complicated to be understandable. Eventually, I noticed that if one
approximated the ideal shape functions of the peaks with an inverse
power law, versus the amplitude of the sum function of Lorentzians,
one could solve for the intersection directly. This was not exactly
at the valley floor, but it was always sufficiently close. This
turned out to be the key approximation, allowing us to see what was
going on globally.

I was hoping that you might also have some ideas about better
mathematical approximations.

To solve even a trivial circuit analytically involves higher level functions
e.g.

https://www.kevinaylward.co.uk/ee/widlarlambert/widlarlambert.xht

I did know of that circuit, but on seeing it again, it reminds me of
Translinear Circuits, invented by Barrie Gilbert. Is Widlar\'s circuit
some kind of special case?

..< https://en.wikipedia.org/wiki/Translinear_circuit >

Its just not worth the effort when simulation just does it all in the wash.

Modern design, for trillions of production ASICs, is performed entirely in
the virtual world.

One can only gain an in-depth understanding of complicated circuits by
simulation.

The tools spit out the relative contribution to phase nose from all
components at any frequency.

This is the key, I think. For optimizing a designs in a relatively
small architecture space, simulation is indeed the way to go, and with
modern computers one can brute-force some pretty complicated
mathematics in reasonable time.

But for exploring far larger spaces, symbolic mathematical methods
(even if approximate) are essential.

One uses a manual Darwinian Algorithm to home in to an optimum. Its the
random generation that makes one seem clever.

I typically run 100,000s of simulations a year in designing ASICs, running a
1000s times faster than in 2000, which is 1000 faster than the early 80s

Yes, Monte Carlo is very good for such things. But understanding the
underlying math is always a good idea:

War story: Some ten years ago, I was involved in an effort to
simulate the load fluctuations that a large radar imposed on its power
source using Monte-Carlo methods. The simulations were very slow, to
the point of stalling progress, but we didn\'t question the speed.

I was in the lab one day, watching the simulation log roll by, and
spotted an information message I had not seen before, but which turned
out to be commonly seen. I didn\'t really think anything of it, but
was bored and curious, and so chased it down.

The message turned out to say that the system matrix being solved was
in effect open-form, and so was being solved by a slow-converging
iterative process, repeated at each and every time step. The
power-system model had been expressed in a pretty-looking
block-diagram language. When we re-coded the power-system model in an
ugly closed form (solvable by matrix inversion without iteration), and
neglected various minor circuits, the simulation ran at least 100
times faster.


Circling back, both simulation and even approximate mathematical
analysis are used, but for different things, and so complement one
another.


Joe Gwinn