M
MM
Guest
I am trying to understand the VHDL structure behind one of the Synopsys flex
models:
(http://www.synopsys.com/products/designware/docs/ds/s/ieee1394a_fx.pdf).
I don't have access to the model itself, only to this datasheet... There is
a VHDL testbench example in this datasheet that shows how the model is
instantiated. Can someone please explain how they did the command interface?
Are these commands (shown in red in the testbench example) VHDL procedures?
If they are how do they communicate to the model? I guess it happens somehow
through a handle, but how do you do it in VHDL? I am intrigued by this
concept...
Thanks,
/Mikhail
models:
(http://www.synopsys.com/products/designware/docs/ds/s/ieee1394a_fx.pdf).
I don't have access to the model itself, only to this datasheet... There is
a VHDL testbench example in this datasheet that shows how the model is
instantiated. Can someone please explain how they did the command interface?
Are these commands (shown in red in the testbench example) VHDL procedures?
If they are how do they communicate to the model? I guess it happens somehow
through a handle, but how do you do it in VHDL? I am intrigued by this
concept...
Thanks,
/Mikhail