Flash memory (Intel StrataFlash J3)

[XSterna]

Hi,

I am having problem using/programming this kind of Flash memory in
VHDL.

I made a simple design to test it but I could not make it run as I
wanted. To be the more accurate in my testing I have decided to test
the "Read identifier Codes" since it is a command that requires 2
cycles : the first one is a write cycle and the second one is the read
cycle.

Here is the link for the datasheet (click on Datasheet View) :
http://www.datasheet4u.com/html/2/8/F/28F256J3_Intel.pdf.html

And here is the code I am using :

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity Flash_controller is
port(
CLK : in std_logic;
Reset : in std_logic;

Flash_data : inout std_logic_vector(15 downto 0);
Flash_addr : out std_logic_vector(23 downto 0);

Flash_rst : out std_logic;
Flash_ce : out std_logic;
Flash_we : out std_logic;
Flash_oe : out std_logic
);
end Flash_controller;

architecture arch_Flash_controller OF Flash_controller IS
signal mem_out : std_logic_vector(15 downto 0);
signal counter_flash : unsigned(4 downto 0);

begin
process(CLK,Reset)
begin
if (Reset = '1') then
counter_flash <= (others => '0');
Flash_rst <= '1';
mem_out <= (others => 'Z');
Flash_ce <= '1';
Flash_we <= '1';
Flash_oe <= '1';
Flash_rst <= '1';
Flash_addr <= (others => 'Z');
Flash_data <= (others => 'Z');

elsif rising_edge(CLK) then
-- T=0
Flash_data <= (others => 'Z');
Flash_addr <=
"0"&"0000"&"0000"&"0000"&"0000"&"0010"&"000";
Flash_ce <= '1';
Flash_we <= '1';
Flash_oe <= '1';
Flash_rst <= '1';
-- T=25
if counter_flash >= 1 and counter_flash <= 6 then
Flash_ce <= '0';
end if;

if counter_flash >= 2 and counter_flash <= 5 then
Flash_we <= '0';
end if;

if counter_flash >= 3 and counter_flash <= 6 then
Flash_data <= "0000"&"0000"&"1001"&"0000";
end if;

if counter_flash >= 8 then
Flash_ce <= '0';
end if;

if counter_flash >= 9 then
Flash_oe <= '0';
end if;

counter_flash <= counter_flash + 1;
end if;

end process;
end arch_Flash_controller;

I agree the use of counter_flash is not really nice but it was the
faster for me to test the flash outside of my main design. The strange
thing is the test for the "Manufacture Code" is working but the test
for the "Device Code" is not. Maybe it is a mistake in my address but
I really work on it ...

To explain a little bit more, I am not cabling the A0 of the flash
since I am using the memory in x16 bits mode. I am using the VHDL
model found on FMF : http://www.freemodelfoundry.com/fmf_models/flash/i28f256j3.vhd

and here are my timing diagrams :
http://rapidshare.com/files/138576963/Timing_Manufact.pdf
http://rapidshare.com/files/138576891/Timing_Device_Code.pdf