flag handling

[Daniel]

Hi Folks

I am just wondering if some guru out there can tell me what is the best

way to implement flags inside a synthesizable VHDL code.

Any one one that?

If so please email me back and share it with all.

Thank you

Faycal

 

[Ralf Hildebrandt]

Daniel wrote:

I am just wondering if some guru out there can tell me what is the best
way to implement flags inside a synthesizable VHDL code.

What do you mean?

A flag is a register. A register is a latch or flipflop while flipflops
are recommended. Flipflops may have synchronous or asynchronos sets and
resets. Synchronous handling is good for design reliability wil
asynchronous operation may offer special behavior and therefore better
performance.
But I guess, that answer is not that, what you have expected...

Ralf

 

[Mike Treseler]

Daniel wrote:

I am just wondering if some guru out there can tell me what is the best
way to implement flags inside a synthesizable VHDL code.

I'm not sure what you mean, but here is one way.

The word "flag" sometimes connotes a register output
bit that is memory-mapped to a bus address and packed in
a specific bit position; read for status, write for control.

Search for read_data_v(0) here:
http://home.comcast.net/~mike_treseler/uart.vhd
for the hardware description of a memory mapped status flag.

Search for valid_handshake_c here:
http://home.comcast.net/~mike_treseler/test_uart.vhd
to see how this flag is used in a simulated read cycle.

-- Mike Treseler