fitting Xilinx CPLD - I/O Pin Termination

[Valentin Tihomirov]

It is not the same as Programmable GND Pins on Unused I/O. I can choose
between Keeper and Float. There is no information about this property.

 

[Klaus Falser]

In article <bopldr$1h0son$1@ID-212430.news.uni-berlin.de>, valentin@abelectron.com says...

It is not the same as Programmable GND Pins on Unused I/O. I can choose
between Keeper and Float. There is no information about this property.

Look at the 'bus bold circuitry' in the XC9500XL date sheet and
at answer #5175 in the Xilinx answer data base.

Best regards
--
Klaus Falser
Durst Phototechnik AG
kfalser@IHATESPAMdurst.it