First Encounter - measuring routing congestion

[RaMbO]

Hi all,
I created a layout from HDL, following a basic design flow: Synopsys'
design_analyzer->First Encounter->Cadence Virtuoso->DRC->LVS.

I was wondering if there was a way to measure wire lengths of a design,
either from the GDS or DEF files.

I'm trying to measure routing congestion that may exist in the
different areas of the core.

Thanks a lot for the help,