FIR FILTER

A

Abbs

Guest
hi.
i have designed a FIR FILTER for 8-taps as an assignment in VHDL. i
have done the required and have almost completed with the design. i
have saved the coeff. values in the LUT ROM and i'am not very much sure
about the scaling accumulator. Scaling accu. is basically used for
round off, but these values are stored in the LUT. We give a 8 bit data
as input to the filter and addition is performed and forms a 4bit data
that is given to the LUT as the address for the coeffecients. Can any
one out here that has understood what i'am trying to explain and can
correct me and help me out by explaiing how to test my design by given
input to the filter and what values should be stored in the LUT.

Thanks
CHEERS
AbbS
 
Abbs wrote:

this group seems not helping...
Click to expand...
I didn't answer because I know something
about vhdl but very little about FIR filters.

Maybe google can find a better group for you:

http://groups.google.com/groups?q=fir+filter+taps+scaling+accumulator

-- Mike Treseler
 
Hi Abbs,
You probably need to be a little more specific with your question. To
me, a scaling accumulator in the context of a FIR filter means a bit
serial approach to a multiplication. Possibly you are trying to
describe a distributed arithmetic filter? www.andraka.com has a good
tutorial on this.

Regarding testing, I would first generate some input samples and pass
them through a Matlab/C/Python/excel implemented FIR filter, and
capture the output samples. Cut and paste the 8 bit numbers into a VHDL
source file and there you pretty much have your test vectors. I am
sure there are heaps of other ways and it depends on how much time you
want to spend....
Regards
Andrew
 
Hi Andrew..

well i'll paste wot i have said in my post which i have posted in other
groups. hope you understand.

i have implemented the FIT FILTER in 2 ways. one that i have described
in my earlier 2 posts, and the next is a simple design, to whihc i ll
paste the VHDL code. its for a 8-tap parallel architecture. the coeff
values are taken in the ROM as constants.
can u just take a look and guide me.


thanks


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;


entity fir_filter is
Port ( clk, reset : in std_logic;
xin : in std_logic_vector(7 downto 0);
yout : out std_logic_vector(15 downto 0));
end fir_filter;


architecture Behavioral of fir_filter is


signal y1, y2, y3, y4 : std_logic_vector(15 downto 0);
signal s1, s2, s3, s4 : std_logic_vector(7 downto 0);
signal r0, r1, r2, r3, r4, r5, r6, r7 : std_logic_vector(7 downto 0);
signal q : std_logic_vector(15 downto 0);
constant h0 : std_logic_vector(7 downto 0) := x"07";
constant h1 : std_logic_vector(7 downto 0) := x"0E";
constant h2 : std_logic_vector(7 downto 0) := x"12";
constant h3 : std_logic_vector(7 downto 0) := x"0E";


begin


process(clk)
begin
if (reset = '1') then
r0 <= "00000000";
r1 <= "00000000";
r2 <= "00000000";
r3 <= "00000000";
r4 <= "00000000";
r5 <= "00000000";
r6 <= "00000000";
r7 <= "00000000";


elsif (clk'event and clk = '1') then
r0 <= xin;
r1 <= r0;
r2 <= r1;
r3 <= r2;
r4 <= r3;
r5 <= r4;
r6 <= r5;
r7 <= r6;
end if;
end process;


process(clk)
begin
if (clk'event and clk = '1') then
s1 <= signed(r0) + signed(r7);
s2 <= signed(r1) + signed(r6);
s3 <= signed(r2) + signed(r5);
s4 <= signed(r3) + signed(r4);
end if;
end process;


process(clk)
begin
if (clk'event and clk = '1') then
y1 <= signed(s1) * signed(h0);
y2 <= signed(s2) * signed(h1);
y3 <= signed(s3) * signed(h2);
y4 <= signed(s4) * signed(h3);


q <= signed(y1) + signed(y2) + signed(y3) + signed(y4);
end if;
end process;
yout <= q;
end Behavioral;



This was a reply to my earlier post by a member:


You should be able to address 8 taps with 3 bits.
The width of your coefficients depends on the multiply-accumulate logic

that you are using. For example, it might have two 8 bit inputs (coef
and data) and a 16 bit accumulator. After you do all eight
multiply-accumulates, you can choose to produce a result with fewer
than 16 bits by rounding. To get down to 8 bits, add 0x0080 and output
the top 8 bits.

John


to which i have replied:

Hi John.
i need some more explanation from your side to understand this better.



You should be able to address 8 taps with 3 bits.
Click to expand...

can u plzz look in this pdf doc.
site : http://www.altera.com/literature/an/an073.pdf

i dont understand this. i'am giving a 8 bit input. which adds up to
give a 4 bit data that is the address to the LUT. the LUT is used for
storing precomputed *sums* of the coefficients - in all combinations
that would be selected according to the data as input address. Table
1, page 4. in the same pdf file.



The width of your coefficients depends on the multiply-accumulate logic
that you are using. For example, it might have two 8 bit inputs (coef
and data) and a 16 bit accumulator. After you do all eight
multiply-accumulates, you can choose to produce a result with fewer
than 16 bits by rounding. To get down to 8 bits, add 0x0080 and output
the top 8 bits.

John
Click to expand...


you saying here that the size of the coeff is depending on the
multiply-accumulate logic, here i dont understand what you mean by
multiply-accumulate logic. is it simillar to the logic thats used in
scaling accumulator? can you please throw some light on scaling
accumulator or what you have mentioned about multiply-acc logic. where
the scalling accumulator is basically done for round off, for over
flow. multiply-acc is used to multiply the input with the coeff value.
this is one of my design that is done in the VHDL and the code is
pasted in the previous posts, in which i'am multiplying the input with
the coeff. and then taking the sum of each multiplier output, then
according to you, i have to round off by adding 0x0080 and then take
the top 8. to be very frank sir, i dint get the idea of adding 0x0080
??? y do we add this? whats the logic behind it. can you plzz explain
this idea (To get down to 8 bits, add 0x0080 ) a little more.
thanks

if u have the time can you please spare few mins looking into the pdf
file i sent and tell me what is actually stored in the LUT, is it the
same that is mentioned in Table 1, page 4. in the pdf doc. This is what

thats really bothering me, and help me get a better idea and
understanding in this design.


thanks a lot


Abbs


hope u understand what i'am designing, and let me know how to proceed.

Thanks
Abbs :)
 
here i dont understand what you mean by
multiply-accumulate logic.
Click to expand...
The multiply-accumulate logic is in your last process- the multiply
part is multiplying the inputs by the coefficients, the accumulate is
adding the results of the multiplications. In DSP-speak, that's
commonly referred to as MAC (Multiply-ACcumulate).

then
according to you, i have to round off by adding 0x0080 and then take
the top 8. to be very frank sir, i dint get the idea of adding 0x0080
Click to expand...
That's the equivalent of adding 0.5 to a positive real number and then
dropping everything to the right of the decimal point, and the result
is then a rounded integer.

I'm sure there are many good textbooks and other sources that help
explain computer number formats, this might be a good starting point:
http://en.wikipedia.org/wiki/Computer_numbering_formats
or
http://www.google.com/search?q=computer+number+formats
 
Hi Abbs,
Write a testbench for your design and you will soon find out if it
works or not.

Synthesize it and you will find out many FPGA resources it uses and how
fast(clock speed) it will run. Does the amount of logic used and speed
meet your design goal/specification?

You probably will find the distributed arithmetic tutorial on
www.andraka.com to be easier to understand than that Altera document. A
fully parallel implementation of a FIR filter uses the most FPGA
resources/logic but can run at the highest sample rate. A serial
implementation uses the least logic but also runs at a slower sample
rate.

You have not mentioned what speed(sample rate) you are trying to
achieve.

Regards
Andrew
 
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