FIR ADDER IMPLEMENTATION

[RealInfo]

Hi all

What is the best FIR ADDER implemntation ?
I mean the unit that adds all mulitlicanion results .

The FIR output is > (Xn * Coefn) + (Xn-1 * Coefn-1) .....+ (Xn-k *
Coefn-k )

So the addition may be done in several ways : Arrray adder , accumulate
adder , synthesiser originated adder of A + B + C +...N .

The point is to make coding easier by avoiding RTL level coding and leting
the synth to do the translation to gate level .

My question is what is the best attitude , RTL coding or synt generated gate
level ?

Thanks in advance

EC

 

[Jonathan Bromley]

On Sun, 8 Feb 2009 16:45:49 +0200, "RealInfo" wrote:

Hi all

What is the best FIR ADDER implemntation ?
I mean the unit that adds all mulitlicanion results .

The FIR output is > (Xn * Coefn) + (Xn-1 * Coefn-1) .....+ (Xn-k *
Coefn-k )

It is usually much better to use a systolic architecture in which
the adders are distributed through the pipeline, and each adder
has only 2 inputs. This is not hard to code. Beware, though:
it makes a large fanout on the data input, typically equal
to the number of stages. Be sure to register the input data
so that your synth tool can do something sensible with the
fanout (register replication, etc).

So the addition may be done in several ways : Arrray adder,
accumulate adder , synthesiser originated adder of A + B + C +...N .

The point is to make coding easier by avoiding RTL level coding
and leting the synth to do the translation to gate level .

Fully agreed. However, particularly if your target is an FPGA, the
systolic architecture makes it MUCH easier for synthesis to do a
good job.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Barry]

On Feb 8, 6:45 am, "RealInfo" <therighti...@yahoo.com> wrote:

Hi all

What is the best FIR ADDER implemntation ?
I mean the unit that adds all mulitlicanion results .

The FIR  output is >  (Xn * Coefn)  +  (Xn-1 * Coefn-1)  .....+ (Xn-k *
Coefn-k )

So the addition may be done in several ways : Arrray adder , accumulate
adder , synthesiser originated adder  of A + B + C +...N  .

The point is to make coding easier by avoiding RTL level coding and leting
the synth to do the translation to gate level .

My question is what is the best attitude , RTL coding or synt generated gate
level ?

Thanks in advance

EC

It seems you are proposing to use the direct form FIR structure which
has a very wide adder (A+B+C+...+N). Instead, you can use the
equivalent transposed form FIR which only has two-input adders between
registers, so it runs at a much higher clock rate. Any good DSP book
will show you what the transposed form looks like - it's quite simple.

Barry

 

On Feb 8, 11:50 am, Barry <barry...@gmail.com> wrote:

On Feb 8, 6:45 am, "RealInfo" <therighti...@yahoo.com> wrote:



Hi all

What is the best FIR ADDER implemntation ?
I mean the unit that adds all mulitlicanion results .

The FIR  output is >  (Xn * Coefn)  +  (Xn-1 * Coefn-1)  ......+ (Xn-k *
Coefn-k )

So the addition may be done in several ways : Arrray adder , accumulate
adder , synthesiser originated adder  of A + B + C +...N  .

The point is to make coding easier by avoiding RTL level coding and leting
the synth to do the translation to gate level .

My question is what is the best attitude , RTL coding or synt generated gate
level ?

Thanks in advance

EC

It seems you are proposing to use the direct form FIR structure which
has a very wide adder (A+B+C+...+N).  Instead, you can use the
equivalent transposed form FIR which only has two-input adders between
registers, so it runs at a much higher clock rate.  Any good DSP book
will show you what the transposed form looks like - it's quite simple.

Barry

What are the requirements for your design? While I fully support your
goal of letting the synthesizer do most of the work for you, first you
have to know exactly what it is that you want to build! In many
cases, those annoying, pedestrian implementation considerations or
overall performance problems will force you to get your hands dirty.
For example, to make use of the SIMD mode of a Virtex DSP slice will
probably require manual instantiation, or at least coding to a very
device-specific style that is almost as baroque as the instantiation
you wanted to avoid.

If your data is much slower than the clock, you could use the MAC
serial form for low resource usage. If your data is skinny you may be
able to play tricks with SIMD modes. And so on. I've personally used
lots of for-generate blocks to build a logarithmic adder tree in the
past, but as has been pointed out, there are much better ways than
that old brute-force-and-ignorance FIR.

But ultimately, there is just no way that you will ever get from a
simple VHDL two-line dot product expression to a well-implemented,
optimal-for-your-application FIR filter just by counting on the
synthesizer to do the right thing. At least not yet. You'll have to
roll up your sleeves and get dirty coding

- Kenn