C
Chris Briggs
Guest
I want to find all the regs and outputs in a design that aren't
initialized during reset. What's the easiest way to do this? I use
NC-Verilog to simulate and I was hoping there was a TCL command to do
it but none of the ones that give values (describe and value) can go
through the hierarchy. Is there a way to iterate through it?
Worst case, I can dump to a VCD file and write a script to parse it,
but I'm hoping for an easier way. Anybody have one?
Thanks.
-cb
initialized during reset. What's the easiest way to do this? I use
NC-Verilog to simulate and I was hoping there was a TCL command to do
it but none of the ones that give values (describe and value) can go
through the hierarchy. Is there a way to iterate through it?
Worst case, I can dump to a VCD file and write a script to parse it,
but I'm hoping for an easier way. Anybody have one?
Thanks.
-cb