filled vias?...

J

John Larkin

Guest
Has anyone used filled vias? Epoxy? Copper?

I need thermal conductivity, as in a D2PAK on one side of a board and
a heat sink on the other.
 
torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
Has anyone used filled vias? Epoxy? Copper?

I need thermal conductivity, as in a D2PAK on one side of a board and
a heat sink on the other.
Click to expand...

if you don\'t mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k

https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5
 
On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
Has anyone used filled vias? Epoxy? Copper?

I need thermal conductivity, as in a D2PAK on one side of a board and
a heat sink on the other.

if you don\'t mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k

https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5
Click to expand...

Pure copper is 400!

8 w/m-k is the sort of value you can get from a filled epoxy. I\'d
probably use a plastic via fill, which I understand is cheaper and
will reduce the thermal resistance of a via by 2:1 or some such.

Maybe we can specify heavier plating in the vias too.

Our usual via is about 75 k/w, top to bottom on a board. 200 of them
would be 0.375 k/w, which is OK. Half of that would be better.
 
On 10/08/2023 11:55 am, John Larkin wrote:
On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
Has anyone used filled vias? Epoxy? Copper?

I need thermal conductivity, as in a D2PAK on one side of a board and
a heat sink on the other.

if you don\'t mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k

https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5

Pure copper is 400!

8 w/m-k is the sort of value you can get from a filled epoxy. I\'d
probably use a plastic via fill, which I understand is cheaper and
will reduce the thermal resistance of a via by 2:1 or some such.

Maybe we can specify heavier plating in the vias too.

Our usual via is about 75 k/w, top to bottom on a board. 200 of them
would be 0.375 k/w, which is OK. Half of that would be better.
Click to expand...

Solder?

piglet
 
torsdag den 10. august 2023 kl. 12.55.31 UTC+2 skrev John Larkin:
On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
Has anyone used filled vias? Epoxy? Copper?

I need thermal conductivity, as in a D2PAK on one side of a board and
a heat sink on the other.

if you don\'t mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k

https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5
Pure copper is 400!

8 w/m-k is the sort of value you can get from a filled epoxy. I\'d
probably use a plastic via fill, which I understand is cheaper and
will reduce the thermal resistance of a via by 2:1 or some such.
Click to expand...

you could try it, epoxy filled and plated of over is only ~$23 for 5x 100x100mm pcbs from jlc
 
On Thu, 10 Aug 2023 12:38:05 +0100, piglet <erichpwagner@hotmail.com>
wrote:

On 10/08/2023 11:55 am, John Larkin wrote:
On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
Has anyone used filled vias? Epoxy? Copper?

I need thermal conductivity, as in a D2PAK on one side of a board and
a heat sink on the other.

if you don\'t mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k

https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5

Pure copper is 400!

8 w/m-k is the sort of value you can get from a filled epoxy. I\'d
probably use a plastic via fill, which I understand is cheaper and
will reduce the thermal resistance of a via by 2:1 or some such.

Maybe we can specify heavier plating in the vias too.

Our usual via is about 75 k/w, top to bottom on a board. 200 of them
would be 0.375 k/w, which is OK. Half of that would be better.

Solder?

piglet
Click to expand...

The usual concern is that with via-in-pad, the vias will suck the
solder away from the part. That sounds good to me! I\'d think that
extra solder paste would leave enough on the pads but slurp some down
into the vias. Solder isn\'t a great heat conductor but a filled via
can have half the theta of a hollow one.

We want a field of d2pak fets opposite a copper CPU cooler.
 
torsdag den 10. august 2023 kl. 17.13.21 UTC+2 skrev John Larkin:
On Thu, 10 Aug 2023 12:38:05 +0100, piglet <erichp...@hotmail.com
wrote:
On 10/08/2023 11:55 am, John Larkin wrote:
On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
Has anyone used filled vias? Epoxy? Copper?

I need thermal conductivity, as in a D2PAK on one side of a board and
a heat sink on the other.

if you don\'t mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k

https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5

Pure copper is 400!

8 w/m-k is the sort of value you can get from a filled epoxy. I\'d
probably use a plastic via fill, which I understand is cheaper and
will reduce the thermal resistance of a via by 2:1 or some such.

Maybe we can specify heavier plating in the vias too.

Our usual via is about 75 k/w, top to bottom on a board. 200 of them
would be 0.375 k/w, which is OK. Half of that would be better.

Solder?

piglet
The usual concern is that with via-in-pad, the vias will suck the
solder away from the part. That sounds good to me! I\'d think that
extra solder paste would leave enough on the pads but slurp some down
into the vias. Solder isn\'t a great heat conductor but a filled via
can have half the theta of a hollow one.
Click to expand...

but if the solder pokes out of the via the pcb won\'t sit flat on the heatsink

> We want a field of d2pak fets opposite a copper CPU cooler.

if you want to get fancy, https://www.pcbway.com/blog/PCB_Basic_Information/Copper_Coin_Embedded_PCB_for_Heat_Dissipation_PCB_Knowledge_00c055cb.html
 
On Thu, 10 Aug 2023 08:32:01 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

torsdag den 10. august 2023 kl. 17.13.21 UTC+2 skrev John Larkin:
On Thu, 10 Aug 2023 12:38:05 +0100, piglet <erichp...@hotmail.com
wrote:
On 10/08/2023 11:55 am, John Larkin wrote:
On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
Has anyone used filled vias? Epoxy? Copper?

I need thermal conductivity, as in a D2PAK on one side of a board and
a heat sink on the other.

if you don\'t mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k

https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5

Pure copper is 400!

8 w/m-k is the sort of value you can get from a filled epoxy. I\'d
probably use a plastic via fill, which I understand is cheaper and
will reduce the thermal resistance of a via by 2:1 or some such.

Maybe we can specify heavier plating in the vias too.

Our usual via is about 75 k/w, top to bottom on a board. 200 of them
would be 0.375 k/w, which is OK. Half of that would be better.

Solder?

piglet
The usual concern is that with via-in-pad, the vias will suck the
solder away from the part. That sounds good to me! I\'d think that
extra solder paste would leave enough on the pads but slurp some down
into the vias. Solder isn\'t a great heat conductor but a filled via
can have half the theta of a hollow one.

but if the solder pokes out of the via the pcb won\'t sit flat on the heatsink
Click to expand...

I don\'t want to do that. We\'ll have a 3G gap-pad between the cooler
and the PCB to get good thermals and compensate for minor mechanical
issues.

The Dynatron G199 cooler is, well, cool. It\'s big and flat.


We want a field of d2pak fets opposite a copper CPU cooler.

if you want to get fancy, https://www.pcbway.com/blog/PCB_Basic_Information/Copper_Coin_Embedded_PCB_for_Heat_Dissipation_PCB_Knowledge_00c055cb.html
Click to expand...
 
On Thu, 10 Aug 2023 08:46:25 -0700, John Larkin
<jlarkin@highlandSNIPMEtechnology.com> wrote:

On Thu, 10 Aug 2023 08:32:01 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

torsdag den 10. august 2023 kl. 17.13.21 UTC+2 skrev John Larkin:
On Thu, 10 Aug 2023 12:38:05 +0100, piglet <erichp...@hotmail.com
wrote:
On 10/08/2023 11:55 am, John Larkin wrote:
On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
Has anyone used filled vias? Epoxy? Copper?

I need thermal conductivity, as in a D2PAK on one side of a board and
a heat sink on the other.

if you don\'t mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k

https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5

Pure copper is 400!

8 w/m-k is the sort of value you can get from a filled epoxy. I\'d
probably use a plastic via fill, which I understand is cheaper and
will reduce the thermal resistance of a via by 2:1 or some such.

Maybe we can specify heavier plating in the vias too.

Our usual via is about 75 k/w, top to bottom on a board. 200 of them
would be 0.375 k/w, which is OK. Half of that would be better.

Solder?

piglet
The usual concern is that with via-in-pad, the vias will suck the
solder away from the part. That sounds good to me! I\'d think that
extra solder paste would leave enough on the pads but slurp some down
into the vias. Solder isn\'t a great heat conductor but a filled via
can have half the theta of a hollow one.

but if the solder pokes out of the via the pcb won\'t sit flat on the heatsink
Click to expand...

My production people say that they can screen a bigger footprint of
solder paste than the part. When it reflows, the extra solder will be
sucked in, to fill the vias without making a bad joint to the part.

That will mostly fill the vias but leaves the hazard of bumps on the
cooler side.
 
torsdag den 10. august 2023 kl. 22.14.18 UTC+2 skrev John Larkin:
On Thu, 10 Aug 2023 08:46:25 -0700, John Larkin
jla...@highlandSNIPMEtechnology.com> wrote:

On Thu, 10 Aug 2023 08:32:01 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 10. august 2023 kl. 17.13.21 UTC+2 skrev John Larkin:
On Thu, 10 Aug 2023 12:38:05 +0100, piglet <erichp...@hotmail.com
wrote:
On 10/08/2023 11:55 am, John Larkin wrote:
On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
Has anyone used filled vias? Epoxy? Copper?

I need thermal conductivity, as in a D2PAK on one side of a board and
a heat sink on the other.

if you don\'t mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k

https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5

Pure copper is 400!

8 w/m-k is the sort of value you can get from a filled epoxy. I\'d
probably use a plastic via fill, which I understand is cheaper and
will reduce the thermal resistance of a via by 2:1 or some such.

Maybe we can specify heavier plating in the vias too.

Our usual via is about 75 k/w, top to bottom on a board. 200 of them
would be 0.375 k/w, which is OK. Half of that would be better.

Solder?

piglet
The usual concern is that with via-in-pad, the vias will suck the
solder away from the part. That sounds good to me! I\'d think that
extra solder paste would leave enough on the pads but slurp some down
into the vias. Solder isn\'t a great heat conductor but a filled via
can have half the theta of a hollow one.

but if the solder pokes out of the via the pcb won\'t sit flat on the heatsink
My production people say that they can screen a bigger footprint of
solder paste than the part. When it reflows, the extra solder will be
sucked in, to fill the vias without making a bad joint to the part.

That will mostly fill the vias but leaves the hazard of bumps on the
cooler side.
Click to expand...

https://designertools.app.protoexpress.com/?appid=TRESVIA&data=ONsTAS5bIR5nFHqIuoQIEqpeYI6FNtC1kNPK9gKk14INuL5nZePBvOxvbHPnk5%20cnHE%20LdwaQf3NPMrsZsHzKD%20%2FM7rjI1AL7TaRuIf%20k%2FaLF5w5yX8NdWEca2p4jr%2Fqd%2F3jiCq2vt109mcdP9itFqb25bcJfU80I08FAEkspybHJoOJbTfc%2FCoK4ZEe1vozrLfjq9Dfs2X42lXYJUnGyJi%20eJFcIvDOZINfUJtZF81UttQPqGh3kPEVQTVWItcA67vr3TNP%20WeEN22%20bXT7AER4Z2z2hsmst3QN4FxVwxvTJQoSn0PzSIu7GDixipPk0cwhm3SBk3Vu9L4HLMaXYQ%3D%3D&q=Thu%20Aug%2010%2016:07:45%20PDT%202023
 
On Wednesday, August 9, 2023 at 7:45:14 PM UTC-7, John Larkin wrote:
Has anyone used filled vias? Epoxy? Copper?

I need thermal conductivity, as in a D2PAK on one side of a board and
a heat sink on the other.
Click to expand...

Why not drill a hole, and fill it with an aluminum nitride slug? You know
you want to.
DPAK or TO220 would work better: more area to plop a bigger slug.

Alternate approaches include just wiring to the transistor with stranded copper,
and letting the heatsink go electrically hot.
 
On Thu, 10 Aug 2023 16:10:31 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

torsdag den 10. august 2023 kl. 22.14.18 UTC+2 skrev John Larkin:
On Thu, 10 Aug 2023 08:46:25 -0700, John Larkin
jla...@highlandSNIPMEtechnology.com> wrote:

On Thu, 10 Aug 2023 08:32:01 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 10. august 2023 kl. 17.13.21 UTC+2 skrev John Larkin:
On Thu, 10 Aug 2023 12:38:05 +0100, piglet <erichp...@hotmail.com
wrote:
On 10/08/2023 11:55 am, John Larkin wrote:
On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
Has anyone used filled vias? Epoxy? Copper?

I need thermal conductivity, as in a D2PAK on one side of a board and
a heat sink on the other.

if you don\'t mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k

https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5

Pure copper is 400!

8 w/m-k is the sort of value you can get from a filled epoxy. I\'d
probably use a plastic via fill, which I understand is cheaper and
will reduce the thermal resistance of a via by 2:1 or some such.

Maybe we can specify heavier plating in the vias too.

Our usual via is about 75 k/w, top to bottom on a board. 200 of them
would be 0.375 k/w, which is OK. Half of that would be better.

Solder?

piglet
The usual concern is that with via-in-pad, the vias will suck the
solder away from the part. That sounds good to me! I\'d think that
extra solder paste would leave enough on the pads but slurp some down
into the vias. Solder isn\'t a great heat conductor but a filled via
can have half the theta of a hollow one.

but if the solder pokes out of the via the pcb won\'t sit flat on the heatsink
My production people say that they can screen a bigger footprint of
solder paste than the part. When it reflows, the extra solder will be
sucked in, to fill the vias without making a bad joint to the part.

That will mostly fill the vias but leaves the hazard of bumps on the
cooler side.

https://designertools.app.protoexpress.com/?appid=TRESVIA&data=ONsTAS5bIR5nFHqIuoQIEqpeYI6FNtC1kNPK9gKk14INuL5nZePBvOxvbHPnk5%20cnHE%20LdwaQf3NPMrsZsHzKD%20%2FM7rjI1AL7TaRuIf%20k%2FaLF5w5yX8NdWEca2p4jr%2Fqd%2F3jiCq2vt109mcdP9itFqb25bcJfU80I08FAEkspybHJoOJbTfc%2FCoK4ZEe1vozrLfjq9Dfs2X42lXYJUnGyJi%20eJFcIvDOZINfUJtZF81UttQPqGh3kPEVQTVWItcA67vr3TNP%20WeEN22%20bXT7AER4Z2z2hsmst3QN4FxVwxvTJQoSn0PzSIu7GDixipPk0cwhm3SBk3Vu9L4HLMaXYQ%3D%3D&q=Thu%20Aug%2010%2016:07:45%20PDT%202023
Click to expand...

Fun. If I specify one via, the theta per via is different from the
theta for the array of one via. Theta also depends on which pattern
that one via is arranged in.

This reminds me of some trace impedance calculators that go negative
for wide traces.
 
On Friday, August 11, 2023 at 9:35:25 AM UTC+10, John Larkin wrote:
On Thu, 10 Aug 2023 16:10:31 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:
torsdag den 10. august 2023 kl. 22.14.18 UTC+2 skrev John Larkin:
On Thu, 10 Aug 2023 08:46:25 -0700, John Larkin <jla...@highlandSNIPMEtechnology.com> wrote:
On Thu, 10 Aug 2023 08:32:01 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:
torsdag den 10. august 2023 kl. 17.13.21 UTC+2 skrev John Larkin:
On Thu, 10 Aug 2023 12:38:05 +0100, piglet <erichp...@hotmail.com> wrote:
On 10/08/2023 11:55 am, John Larkin wrote:
On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:
torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
Click to expand...

<snip>
> This reminds me of some trace impedance calculators that go negative for wide traces.

That\'s what happens when you mindlessly apply a simple formula to a trace wider than the formula was designed to cope with.

I\'ve got Peter Yip\'s book \":High Frequency Circuit design and Management\" ISBN 0-412-34160-3 which devotes a chapter to microstrip and has two fairly elaborate formulae for wide and narrow microstrip. The crossover point is at a characteristic impedance of about 35R. ECL application notes use a simpler formula which works well enough for lines between 50R and 75R.

It wildly wrong for wider traces

--
Bill Sloman, Sydney
 
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