file include in VHDL

[anupam]

hi,

I am in verification using VHDL . I want to write a single testbench
,for a block and run different test cases using it , but the file
include function is not present in VHDL so whats the easier method to
do the same??

regards,
Anupam Jain

 

[Reiner Huober]

1. anupam
6 Feb. 11:46 Optionen anzeigen

Newsgroups: comp.lang.vhdl
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Datum: 6 Feb 2006 02:46:12 -0800
Lokal: Mo 6 Feb. 2006 11:46
Betreff: file include in VHDL
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hi,

I am in verification using VHDL . I want to write a >single testbench
,for a block and run different test cases using it , >but the file
include function is not present in VHDL so whats >the easier method to
do the same??

Some use the C preprocessor before compiling.

The standard way is to create different architectures for the tester
entity in the testbench and use VHDL configurations to select a
specific architecture for each test.

Hubble

 

[Mike Treseler]

anupam wrote:

I want to write a single testbench
,for a block and run different test cases using it , but the file
include function is not present in VHDL so whats the easier method to
do the same??

I use procedures.
See the reference testbench here for an example:
http://home.comcast.net/~mike_treseler/

-- Mike Treseler

 

[anupam]

Not of much use
The entity part of my testbench is empty like any other testbench
so i am writin g the whole testbench when i am writing a new
architecture .....


regards,
Anupam jain

 

[anupam]

hi,
Procedures work fine if you are verifing a standard algorithm or
protocol but this approach doesnt work with random stimuli ....


regards.
Anupam Jain

 

[Mike Treseler]

anupam wrote:

Procedures work fine if you are verifing a standard algorithm or
protocol but this approach doesnt work with random stimuli ....

A testbench can only handle a finite
set of stimulus data, "random" or otherwise.
Your choices to convert an acquired
data file to vhdl constants are:

1. Convert all the data samples to
a vhdl constant array package using a script
or editor macro.

2. Convert your data samples to
vhdl variables on the fly using vhdl textio.

I find that (1) is clean and simple and
(2) is slow and annoying.

The only use I can imagine for a
pre-processor would be to select one of
the data samples.

Instead of a pre-processor, I
would convert all of the samples
into one vhdl package and make the
sample number an array index.
Good luck.

-- Mike Treseler