Figure Causing Multiple Stamped Connections

B

Balavelan

Guest
Hi,

I am university student currently learning Cadence tools. I use DIVA for
DRC, Extract and LVS.

Process : TSMC18RF (0.18um)

I am currently doing layout of an 10 phase oscillator circuit. When I run
DRC on my completed layout I get no errors. When I run Extract with the
"Join nets with same name" switch ON and Parasitic RC Switch SET. I get the
following errors:

Figure Causing Multiple Stamped Connections
Figure Having Multiple Stamped Connections

if i set the Parasitic RC switch OFF - that is if don't set any switches (
no parasitic extract ) I DON'T get these errors or ANY errors.

My Design also passes the LVS successfully

my design has following layout structure:

VDD Rail
====================
BUFFER Amplifiers
====================
GND Rail
====================
Differential Amplifiers
====================
VDD Rail
====================
Buffer Amplifiers
====================
GND Rail
====================

I googled these error messages and I found some explanations but I don't
seem to violate any that is mentioned in these explanations. Like I have
connected the GND and VDD properly.

the divaEXT doesn't like me putting 2 separate ground Contacts. my Ground
contacts are M1_SUB. if put them at separate places i get this error. How do
I go about resolving this issue? please help.

Balavelan
 
On Thu, 16 Feb 2006 17:15:33 +1000, "Balavelan" <velan@itee.uq.edu.au> wrote:

Hi,

I am university student currently learning Cadence tools. I use DIVA for
DRC, Extract and LVS.

Process : TSMC18RF (0.18um)

I am currently doing layout of an 10 phase oscillator circuit. When I run
DRC on my completed layout I get no errors. When I run Extract with the
"Join nets with same name" switch ON and Parasitic RC Switch SET. I get the
following errors:

Figure Causing Multiple Stamped Connections
Figure Having Multiple Stamped Connections

if i set the Parasitic RC switch OFF - that is if don't set any switches (
no parasitic extract ) I DON'T get these errors or ANY errors.

My Design also passes the LVS successfully

my design has following layout structure:

VDD Rail
====================
BUFFER Amplifiers
====================
GND Rail
====================
Differential Amplifiers
====================
VDD Rail
====================
Buffer Amplifiers
====================
GND Rail
====================

I googled these error messages and I found some explanations but I don't
seem to violate any that is mentioned in these explanations. Like I have
connected the GND and VDD properly.

the divaEXT doesn't like me putting 2 separate ground Contacts. my Ground
contacts are M1_SUB. if put them at separate places i get this error. How do
I go about resolving this issue? please help.

Balavelan
Click to expand...
If you have multiple ground contacts, are they tied together with metal, or do
they connected to pins with the same name (given that you have the "Join nets
with same name turned on)? Most likely (without having looked at the rules),
they're using this to ensure that you don't supply circuitry through the
substrate - and so all connections down onto the substrate (or each well) are
connected in metal. Otherwise each connection stamps a different net onto the
substrate, which is a conducting layer...

Regards,

Andrew.
 
Thanks Andrew for ur reply.

I have metal Layers running over the contacts. I haven't connected the
2 separate ground contacts using a metal. I have them connected to a
PIN and I have the switch "Join nets with same name turned ON".

I tested this error for a simple case. I made a fresh layout with two
separate Metal 1 Strips and put the M1_SUB or the M1_PACTIVE contacts.
Whether I connect these 2 strips using Metal 1 again or just connecting
them tio a PIN with the Switch appropriately turned ON, both dont make
a diference. I get the same error.

if I have say 2 inverters layout where the structure is:

===============
VDD | |------> VDD Pin
===============
Inverter1
===============
GND | |------>GND Pin
===============
inverter2
===============
VDD | |----> VDD Pin
===============

if i do the Extract with switch "Join nets with same PIN Name" ON

I dont get any errorfor the situation above, but If for example I put
another inverter "Inverter 3" below Inverter 2.
which looks like:

===============
VDD | |------> VDD Pin
===============
Inverter1
===============
GND | |------>GND Pin
===============
inverter2
===============
VDD | |----> VDD Pin
===============
inverter3
===============
GND | |------>GND Pin
===============

then I get the Errors I said before. even if i connect the 2 ground and
2 vdd using appropriate metal, I get the error. the markers dont
explain anything further in this. I am not able to relate the
explanations that I found in previous discussions in different forums
with the situation I am in now. Since I m learnig Layout now, please
help me with suggestions as what I should be doing now. Is there
anything I have to do in the divaEXT.rul file or is there any layout
practice I am not doing which leads to this error ?
 
hi,

i am having the similar error too. I am using 18um technology and I
have layout an op-amp and a capacitor (using nmoscap).
Both op-amp and capacitor passed the DRC check and Parasitic RC switch
extraction if they place on 2 seperate cell view. but when i try to put
the op-amp and capacitor layout (with/without connection) together on
the same cellview, it can only pass the DRC check but not the parasitic
extraction.

P.S most of my classmate are having the same problem.
please help
thanks alot
 
On 18 Mar 2006 15:30:21 -0800, chunling.lau@gmail.com wrote:

hi,

i am having the similar error too. I am using 18um technology and I
have layout an op-amp and a capacitor (using nmoscap).
Both op-amp and capacitor passed the DRC check and Parasitic RC switch
extraction if they place on 2 seperate cell view. but when i try to put
the op-amp and capacitor layout (with/without connection) together on
the same cellview, it can only pass the DRC check but not the parasitic
extraction.

P.S most of my classmate are having the same problem.
please help
thanks alot
Click to expand...
I'm not sure what similar error you are referring to. It would help if
you include the message you are responding to since old messages get
purged off of some news servers.

I expect your problem is being caused by the power distribution metals
being broken into multiple nets by the resistance analysis. This puts
each well and substrate tie in a different net and the geomStamp gives
these errors.

The solution is for the Parasitic RC switch to cause a geomStamp without
the error option to be used.
 
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