Fighting against Layout XL Connectivity

[Allan Wang]

I have a layout for series resistors with instance names like:

|R1 |R2 |R3 |R4

In my schematic I have four resistors with the nets inbetween named
t0, t1, t2. I have the connectivity of these nets well defined in
Layout XL.

I go to Connectivity->Check->Against Source, and it says there are 0
differences. Then I go to Connectivity->Update->Components and Nets
and hit OK. You'd think it wouldn't actually do anything right? Well,
it changes my layout instance names to:

|R1 |R3 |R2 |R4

And the routing is no longer in series. When I manually change the
names back and hit update again, it repeats this. If I try to outsmart
it by making my schematic R1, R3, R2, R4, and then I hit update, my
layout automatically becomes R1, R2, R3, R4 and the routing is still
messed up. For some reason it's insisting on forcing the layout
instances to be in this order. This even happens when I delete all net
connectivity information from the layout before trying to update.
Anyone knows what is going on here?

 

By the way, I tried this on both 6.1.4 and 6.1.5.500.3 and I get the same results.

Allan

On Tuesday, March 20, 2012 2:33:01 PM UTC-4, Allan Wang wrote:

I have a layout for series resistors with instance names like:

|R1 |R2 |R3 |R4

In my schematic I have four resistors with the nets inbetween named
t0, t1, t2. I have the connectivity of these nets well defined in
Layout XL.

I go to Connectivity->Check->Against Source, and it says there are 0
differences. Then I go to Connectivity->Update->Components and Nets
and hit OK. You'd think it wouldn't actually do anything right? Well,
it changes my layout instance names to:

|R1 |R3 |R2 |R4

And the routing is no longer in series. When I manually change the
names back and hit update again, it repeats this. If I try to outsmart
it by making my schematic R1, R3, R2, R4, and then I hit update, my
layout automatically becomes R1, R2, R3, R4 and the routing is still
messed up. For some reason it's insisting on forcing the layout
instances to be in this order. This even happens when I delete all net
connectivity information from the layout before trying to update.
Anyone knows what is going on here?

 

[Jean-Marc Bourguet]

Allan Wang <allanvv@gmail.com> writes:

I have a layout for series resistors with instance names like:

|R1 |R2 |R3 |R4

In my schematic I have four resistors with the nets inbetween named
t0, t1, t2. I have the connectivity of these nets well defined in
Layout XL.

I go to Connectivity->Check->Against Source, and it says there are 0
differences. Then I go to Connectivity->Update->Components and Nets
and hit OK. You'd think it wouldn't actually do anything right? Well,
it changes my layout instance names to:

|R1 |R3 |R2 |R4

And the routing is no longer in series. When I manually change the
names back and hit update again, it repeats this. If I try to outsmart
it by making my schematic R1, R3, R2, R4, and then I hit update, my
layout automatically becomes R1, R2, R3, R4 and the routing is still
messed up. For some reason it's insisting on forcing the layout
instances to be in this order. This even happens when I delete all net
connectivity information from the layout before trying to update.
Anyone knows what is going on here?

No. There are years since I last worked with that, but it seems a bug.
But Check Against Source saying nothing while Update Compoments and Nets
doing something is very strange. It is also possible you don't tell us
something which is pertinent (probably without knowing it is, there are
lot of settings in Virtuoso). Some questions in order to try to
eliminate that last possibility.

Do you use a "Physical configuration view" (see in "Update Connectivity
Reference")? Does its content explain what you see?

After Check Against Source but before Update Compoments and Nets, does
cross-selection shows what you are expecting?

Is there any other connectivity in place with those resistors or are
they just connected in serie without any other connection?

Is there a difference of parameters and resistor kinds? Are the value of
"parameters to ignore during check" and "parameters to ignore during
generation and update" in the "Parameters" pane of XL option form
consistent?

Yours,

--
Jean-Marc