J
Juan
Guest
I need some quick help:
I am using the independent clock FIFO supplied by Xilinx in xapp175 on my
digilent D2SB board, it is a Spartan 2E(300) with a 50Mhz external clock.
I am using the dll_4x module also supplied by xilinx in an xapp to generate
2x(100Mhz) and 4x(200Mhz) clocks.
The fifo works fine when driven with 50Mhz read and write clocks. However,
I want to write at 100Mhz and read at 50Mhz. Whenever I attempt this, i am
getting corrupt data through the fifo...either i am loosing data or
duplicating it. Is 100Mhz too much to expect from this configuration, or is
there something wrong with my design? I am using the exact same code that
works at 50Mhz, but I am changing the write clock port map on the fifo to
100Mhz, as well as the clock of the process which generates data to write to
the fifo. The process just generates a simple data pattern, and feeds a
byte to the fifo if it is not full on that clock.
The only curious note is that the FIFO module has BUFG's on both clock
inputs, and it wouldn't compile with the BUFG's in place. I had to remove
them and then it would compile fine. If I left the BUFG's in place it would
give me multiple 'illegal' connection errors.
Any help would be greatly appreciated.
Juan
I am using the independent clock FIFO supplied by Xilinx in xapp175 on my
digilent D2SB board, it is a Spartan 2E(300) with a 50Mhz external clock.
I am using the dll_4x module also supplied by xilinx in an xapp to generate
2x(100Mhz) and 4x(200Mhz) clocks.
The fifo works fine when driven with 50Mhz read and write clocks. However,
I want to write at 100Mhz and read at 50Mhz. Whenever I attempt this, i am
getting corrupt data through the fifo...either i am loosing data or
duplicating it. Is 100Mhz too much to expect from this configuration, or is
there something wrong with my design? I am using the exact same code that
works at 50Mhz, but I am changing the write clock port map on the fifo to
100Mhz, as well as the clock of the process which generates data to write to
the fifo. The process just generates a simple data pattern, and feeds a
byte to the fifo if it is not full on that clock.
The only curious note is that the FIFO module has BUFG's on both clock
inputs, and it wouldn't compile with the BUFG's in place. I had to remove
them and then it would compile fine. If I left the BUFG's in place it would
give me multiple 'illegal' connection errors.
Any help would be greatly appreciated.
Juan