fifo interface design

i want to read & write data to/from a fifo placed in fpga. MCU's
external bus is connected to the chip. I am using the sync-fifo ip of
Altera CycloneII. The data bus and control signal are connected to
fifo directly. it's unfortune that when i read once from bus, data
would be read twice from fifo because there are two clock rising edges
during read signal(low active) is resetted. I think it will read more
datas from fifo if the read signal is resetted long enough.
Is there any good design for fifo interface connecting on the
exteranl bus?

As I understand your problem, you need to read the FIFO only once
after each edge of the incoming "read" signal, so you must detect the
leading edge of that signal and read only at that time. You can do
this by considering repeatedly the state of the incoming signal and
its "previous" state (the state read at the time of the last internal
clock).

Since your incoming "read" signal is likely to be asynchronous to the
internal clock, you should also consider the problem of
"metastability", which is discussed in detail elsewhere.

Mike

 

[Readon]

i want to read & write data to/from a fifo placed in fpga. MCU's
external bus is connected to the chip. I am using the sync-fifo ip of
Altera CycloneII. The data bus and control signal are connected to
fifo directly. it's unfortune that when i read once from bus, data
would be read twice from fifo because there are two clock rising edges
during read signal(low active) is resetted. I think it will read more
datas from fifo if the read signal is resetted long enough.
Is there any good design for fifo interface connecting on the
exteranl bus?