H
Hari
Guest
Hi,
I have an automatically generated code from some source
"cztgen.exe". I am working on performing FFT (C-Z Tfranform).The code
basically has filter (FIR)coefficient computation and convolution .I
am using two other
code to perform multiplication and
store coefficient/twiddle factors(not that of filter). My problem is I
am not getting write answers when i simulate the codes.The multiplier
and coefficent(not that of filter) codes are working fine. When put
together, I don't get right answer. I suspect there is some problem
with the filter coefficent code.
How do I check the code? and where can I find the source for the
filter coeff. code.Thank you.
Hari
PS: here's the code for reference.
-- This is the 16-point CZT FSM and FIR filter
-- automatic generated with cztgen.exe -- DO NOT EDIT!
-- The filter has 4 real and 4 imaginary different coefficients
-- Coefficient bits = 16 Data bits = 16
-- OVL guard bits = 0 LSB guard bits = 4
-- Scale Multiplier = 2048 Scale FIR = 16
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_signed.ALL;
ENTITY czr16s16o0g4h IS ------> Interface
GENERIC (Wfir: INTEGER := 20; -- Filter accu bit width
Lfir: INTEGER := 31; -- Filter length = 2*DFTlenght-1
W1 : INTEGER := 4; -- log2(DFT length)
W : INTEGER := 16); -- Data/Coeff bit width
PORT ( clk : IN STD_LOGIC;
x_real_in, x_imag_in : IN STD_LOGIC_VECTOR(W-1 DOWNTO 0);
valid_in : OUT STD_LOGIC;
t1_real_out,t1_imag_out, ccmul_r_out,t2_real_out,t2_imag_out,
ccmul_i_out : OUT STD_LOGIC_VECTOR(W-1 DOWNTO 0);
countn : OUT integer range 0 to 100;
r0_out, i0_out : OUT STD_LOGIC_VECTOR(W-1 DOWNTO 0);
sxtxr_out, sxtxi_out : OUT STD_LOGIC_VECTOR(Wfir-1 DOWNTO 0);
valid_out : OUT STD_LOGIC;
y_real, y_imag : OUT STD_LOGIC_VECTOR(W-1 DOWNTO 0));
END czr16s16o0g4h;
ARCHITECTURE flex OF czr16s16o0g4h IS
COMPONENT d16b16
PORT ( t_in : IN STD_LOGIC_VECTOR(4-1 DOWNTO 0);
re_out : OUT STD_LOGIC_VECTOR(16-1 DOWNTO 0);
im_out : OUT STD_LOGIC_VECTOR(16-1 DOWNTO 0));
END COMPONENT;
COMPONENT cmi3a5b16
GENERIC (W2 : INTEGER := 33; -- Multiplier bit width
W1 : INTEGER := 17; -- Bit width c+s sum
W : INTEGER := 16); -- Input bit width
PORT (clk : STD_LOGIC; -- Clock for the output register
x_in, y_in : IN STD_LOGIC_VECTOR(W-1 DOWNTO 0);
c_in, s_in : IN STD_LOGIC_VECTOR(W-1 DOWNTO 0);
r_out, i_out : OUT STD_LOGIC_VECTOR(W-1 DOWNTO 0));
END COMPONENT;
SIGNAL count : integer RANGE 0 TO 63;
TYPE STATE_TYPE IS (Start, Load, Run);
SIGNAL state : STATE_TYPE ;
SIGNAL x_real, x_imag : STD_LOGIC_VECTOR(W-1 DOWNTO 0);
SUBTYPE WORD IS INTEGER;-- RANGE -2**19 TO 2**19-1;
SIGNAL mr0, mi0, real0, imag0 : WORD; -- Tapped delay line
SIGNAL mr1, mi1, real1, imag1 : WORD; -- Tapped delay line
SIGNAL mr2, mi2, real2, imag2 : WORD; -- Tapped delay line
SIGNAL mr3, mi3, real3, imag3 : WORD; -- Tapped delay line
SIGNAL mr4, mi4, real4, imag4 : WORD; -- Tapped delay line
SIGNAL mr5, mi5, real5, imag5 : WORD; -- Tapped delay line
SIGNAL mr6, mi6, real6, imag6 : WORD; -- Tapped delay line
SIGNAL mr7, mi7, real7, imag7 : WORD; -- Tapped delay line
SIGNAL mr8, mi8, real8, imag8 : WORD; -- Tapped delay line
SIGNAL mr9, mi9, real9, imag9 : WORD; -- Tapped delay line
SIGNAL mr10, mi10, real10, imag10 : WORD; -- Tapped delay line
SIGNAL mr11, mi11, real11, imag11 : WORD; -- Tapped delay line
SIGNAL mr12, mi12, real12, imag12 : WORD; -- Tapped delay line
SIGNAL mr13, mi13, real13, imag13 : WORD; -- Tapped delay line
SIGNAL mr14, mi14, real14, imag14 : WORD; -- Tapped delay line
SIGNAL mr15, mi15, real15, imag15 : WORD; -- Tapped delay line
SIGNAL mr16, mi16, real16, imag16 : WORD; -- Tapped delay line
SIGNAL mr17, mi17, real17, imag17 : WORD; -- Tapped delay line
SIGNAL mr18, mi18, real18, imag18 : WORD; -- Tapped delay line
SIGNAL mr19, mi19, real19, imag19 : WORD; -- Tapped delay line
SIGNAL mr20, mi20, real20, imag20 : WORD; -- Tapped delay line
SIGNAL mr21, mi21, real21, imag21 : WORD; -- Tapped delay line
SIGNAL mr22, mi22, real22, imag22 : WORD; -- Tapped delay line
SIGNAL mr23, mi23, real23, imag23 : WORD; -- Tapped delay line
SIGNAL mr24, mi24, real24, imag24 : WORD; -- Tapped delay line
SIGNAL mr25, mi25, real25, imag25 : WORD; -- Tapped delay line
SIGNAL mr26, mi26, real26, imag26 : WORD; -- Tapped delay line
SIGNAL mr27, mi27, real27, imag27 : WORD; -- Tapped delay line
SIGNAL mr28, mi28, real28, imag28 : WORD; -- Tapped delay line
SIGNAL mr29, mi29, real29, imag29 : WORD; -- Tapped delay line
SIGNAL mr30, mi30, real30, imag30 : WORD; -- Tapped delay line
-----******** Real and imaginary filter coefficients computed with
RAG:
SIGNAL xr1, xi1 : WORD;
SIGNAL xr31, xi31 : WORD;
SIGNAL xr97, xi97 : WORD;
SIGNAL xr125, xi125 : WORD;
SIGNAL xr251, xi251 : WORD;
SIGNAL xr399, xi399 : WORD;
SIGNAL xr799, xi799 : WORD;
SIGNAL xr4017, xi4017 : WORD;
SIGNAL xr6393, xi6393 : WORD;
SIGNAL xr11585, xi11585 : WORD;
SIGNAL xr11973, xi11973 : WORD;
SIGNAL xr16069, xi16069 : WORD;
SIGNAL xr23170, xi23170 : WORD;
SIGNAL xr32138, xi32138 : WORD;
SIGNAL xr32768, xi32768 : WORD;
-- Auxiliary signal definitions
SIGNAL t1_in,t2_in :
STD_LOGIC_VECTOR(W1-1 DOWNTO 0);
SIGNAL real_in, imag_in : STD_LOGIC_VECTOR(W-1
DOWNTO 0);
SIGNAL t1_real, t1_imag,t2_real,t2_imag : STD_LOGIC_VECTOR(W-1
DOWNTO 0);
SIGNAL ccmul_r, ccmul_i : STD_LOGIC_VECTOR(W-1
DOWNTO 0);
SIGNAL sxtxr, sxtxi : STD_LOGIC_VECTOR(Wfir-1
DOWNTO 0);
SIGNAL r0, i0 : STD_LOGIC_VECTOR(W-1
DOWNTO 0);
SIGNAL y_r, y_i : STD_LOGIC_VECTOR(W-1
DOWNTO 0);
BEGIN
States: PROCESS ------> State machine for CZT filter
BEGIN
WAIT UNTIL clk = '1';
CASE state IS
WHEN Start => -- Initialization step
state <= Load;
count <= 0;
t1_in <= "0000"; -- Reset tables
t2_in <= "0000";
WHEN Load => -- Multiply inputs with twiddle factors
IF count = 17 THEN -- Load phase done ?
state <= Run;
ELSE
state <= Load;
t1_in <= t1_in + "0001";
END IF;
-- IF count < 16 THEN
-- t1_in<=t1_in+"0001";
-- ELSE
-- t1_in<="0000";
-- END IF;
count<=count+1;
countn<=count;
WHEN Run => -- Multiply filter output with twiddle factors
IF count = 47 THEN -- Run phase done ?
state <= Start; -- Output of result
t1_in <= "0000"; -- Reset tables
ELSE -- and start again
state <= Run;
t2_in <= t2_in + "0001";
END IF;
count<=count+1;
countn<=count;
IF count > 19 AND count < 36 THEN
valid_out <= '1';
y_real <= y_r;--ccmul_r;
y_imag <= y_i;--ccmul_i;
ELSE
valid_out <= '0';
y_real <= (OTHERS => '0');
y_imag <= (OTHERS => '0');
END IF;
IF count < 15 THEN
valid_in <= '1';
ELSE
valid_in <= '0';
END IF;
END CASE;
END PROCESS States;
-- Note that all signals: xrXXX, xiXXX are global defined
Coeffs: PROCESS (sxtxr, sxtxi)
VARIABLE xr, xi : WORD;
BEGIN
-- Compute the filter coefficients but use no FFs
xr := CONV_INTEGER(sxtxr);
xi := CONV_INTEGER(sxtxi);
-- rag: Generate even coefficients by shift of fundamentals
xr1 <= xr;
xi1 <= xi;
xr32138 <= xr16069 * 2 / 2048;
xi32138 <= xi16069 * 2 / 2048;
xr23170 <= xr11585 * 2 / 2048;
xi23170 <= xi11585 * 2 / 2048;
xr32768 <= xr1 * 32768 / 2048;
xi32768 <= xi1 * 32768 / 2048;
-- rag: Generate coefficient by mutiplying fundamentals with
power-of-2
xr31 <= xr1 * 32 - xr1 * 1;
xi31 <= xi1 * 32 - xi1 * 1;
xr125 <= xr31 * 4 + xr1 * 1;
xi125 <= xi31 * 4 + xi1 * 1;
xr251 <= xr125 * 2 + xr1 * 1;
xi251 <= xi125 * 2 + xi1 * 1;
xr4017 <= xr251 * 16 + xr1 * 1;
xi4017 <= xi251 * 16 + xi1 * 1;
xr16069 <= xr4017 * 4 + xr1 * 1;
xi16069 <= xi4017 * 4 + xi1 * 1;
xr97 <= xr1 * 128 - xr31 * 1;
xi97 <= xi1 * 128 - xi31 * 1;
xr11973 <= xr16069 * 1 - xr1 * 4096;
xi11973 <= xi16069 * 1 - xi1 * 4096;
xr11585 <= xr11973 * 1 - xr97 * 4;
xi11585 <= xi11973 * 1 - xi97 * 4;
xr399 <= xr31 * 16 - xr97 * 1;
xi399 <= xi31 * 16 - xi97 * 1;
xr799 <= xr399 * 2 + xr1 * 1;
xi799 <= xi399 * 2 + xi1 * 1;
xr6393 <= (xr799 * 8 + xr1 * 1) / 2048;
xi6393 <= (xi799 * 8 + xi1 * 1) / 2048;
-- Comp. Time= 12.000000 sec.
-- Results adder: rag = 22 mag = 20 csd = 26
-- Resources: length extfund = 91 summat = 6546
-- RAG with Add/Sub
-- linput= 4 lcoefft = 3 mag table used = 18 bits
END PROCESS Coeffs;
-- Real and imaginary complex filter coefficients
-- Real part = xr*Coeff.r - xi*Coeff.i
-- Imaginary part = xr*Coeff.i + xi*Coeff.r
Cmuls: PROCESS ( xr32138, xr6393, xr23170, xr32768,
xi32138 ,xi6393 ,xi23170 ,xi32768)
BEGIN -- filters in transposed form
-- WAIT UNTIL clk = '1';
-- no FF for input signals
mr0 <= xr32138 - xi6393; -- sign = +
mi0 <= xr6393 + xi32138; -- = 0.981 +0.195 * i
mr1 <= xr23170 - xi23170; -- sign = +
mi1 <= xr23170 + xi23170; -- = 0.707 +0.707 * i
mr2 <= - xr6393 - xi32138; -- sign = +
mi2 <= xr32138 - xi6393; -- = -0.195 +0.981 * i
mr3 <= - xr32768; -- sign = +
mi3 <= - xi32768; -- = -1.000 +0.000 * i
mr4 <= mr2; -- sign = -
mi4 <= mi2; -- = 0.195 -0.981 * i
mr5 <= mr1; -- sign = +
mi5 <= mi1; -- = 0.707 +0.707 * i
mr6 <= mr0; -- sign = -
mi6 <= mi0; -- = -0.981 -0.195 * i
mr7 <= mr3; -- sign = -
mi7 <= mi3; -- = 1.000 -0.000 * i
mr8 <= mr0; -- sign = -
mi8 <= mi0; -- = -0.981 -0.195 * i
mr9 <= mr1; -- sign = +
mi9 <= mi1; -- = 0.707 +0.707 * i
mr10 <= mr2; -- sign = -
mi10 <= mi2; -- = 0.195 -0.981 * i
mr11 <= mr3; -- sign = +
mi11 <= mi3; -- = -1.000 +0.000 * i
mr12 <= mr2; -- sign = +
mi12 <= mi2; -- = -0.195 +0.981 * i
mr13 <= mr1; -- sign = +
mi13 <= mi1; -- = 0.707 +0.707 * i
mr14 <= mr0; -- sign = +
mi14 <= mi0; -- = 0.981 +0.195 * i
mr15 <= mr3; -- sign = -
mi15 <= mi3; -- = 1.000 -0.000 * i
mr16 <= mr0; -- sign = +
mi16 <= mi0; -- = 0.981 +0.195 * i
mr17 <= mr1; -- sign = +
mi17 <= mi1; -- = 0.707 +0.707 * i
mr18 <= mr2; -- sign = +
mi18 <= mi2; -- = -0.195 +0.981 * i
mr19 <= mr3; -- sign = +
mi19 <= mi3; -- = -1.000 +0.000 * i
mr20 <= mr2; -- sign = -
mi20 <= mi2; -- = 0.195 -0.981 * i
mr21 <= mr1; -- sign = +
mi21 <= mi1; -- = 0.707 +0.707 * i
mr22 <= mr0; -- sign = -
mi22 <= mi0; -- = -0.981 -0.195 * i
mr23 <= mr3; -- sign = -
mi23 <= mi3; -- = 1.000 -0.000 * i
mr24 <= mr0; -- sign = -
mi24 <= mi0; -- = -0.981 -0.195 * i
mr25 <= mr1; -- sign = +
mi25 <= mi1; -- = 0.707 +0.707 * i
mr26 <= mr2; -- sign = -
mi26 <= mi2; -- = 0.195 -0.981 * i
mr27 <= mr3; -- sign = +
mi27 <= mi3; -- = -1.000 +0.000 * i
mr28 <= mr2; -- sign = +
mi28 <= mi2; -- = -0.195 +0.981 * i
mr29 <= mr1; -- sign = +
mi29 <= mi1; -- = 0.707 +0.707 * i
mr30 <= mr0; -- sign = +
mi30 <= mi0; -- = 0.981 +0.195 * i
END PROCESS Cmuls;
Structure: PROCESS --(mr0,mr1,mr2,mr3,mr4,mr5,mr6,mr7,mr8,mr9,mr10,
--
mr11,mr12,mr13,mr14,mr15,mr16,mr17,mr18,mr19,mr20,mr20,mr21,mr22,mr23,
--mr24,mr25,mr26,mr27,mr28,mr29,mr30,mi0,mi1,mi2,mi3,mi4,mi5,mi6,mi7,mi8,
--mi9,mi10,mi11,mi12,mi13,mi14,mi15,mi16,mi17,mi18,mi19,mi20,mi21,mi22,mi23,
--mi24,mi25,mi26,mi27,mi28,mi29,mi30) -- Structure of the two
FIR
BEGIN -- filters in transposed form
WAIT UNTIL clk = '1';
-- FF for input signals
x_real <= x_real_in;
x_imag <= x_imag_in;
-- Real part of FIR filter in transposed form = xr*Coeff.r -
xi*Coeff.i
real0 <= real1 + mr0; -- + xr32138 - xi6393=> 0.981 +0.195 * i
real1 <= real2 + mr1; -- + xr23170 - xi23170=> 0.707 +0.707 * i
real2 <= real3 + mr2; -- - xr6393 - xi32138=> -0.195 +0.981 * i
real3 <= real4 + mr3; -- - xr32768=> -1.000 +0.000 * i
real4 <= real5 - mr4; -- + xr6393 + xi32138=> 0.195 -0.981 * i
real5 <= real6 + mr5; -- + xr23170 - xi23170=> 0.707 +0.707 * i
real6 <= real7 - mr6; -- - xr32138 + xi6393=> -0.981 -0.195 * i
real7 <= real8 - mr7; -- + xr32768=> 1.000 -0.000 * i
real8 <= real9 - mr8; -- - xr32138 + xi6393=> -0.981 -0.195 * i
real9 <= real10 + mr9; -- + xr23170 - xi23170=> 0.707 +0.707 * i
real10 <= real11 - mr10; -- + xr6393 + xi32138=> 0.195 -0.981 *
i
real11 <= real12 + mr11; -- - xr32768=> -1.000 +0.000 * i
real12 <= real13 + mr12; -- - xr6393 - xi32138=> -0.195 +0.981 *
i
real13 <= real14 + mr13; -- + xr23170 - xi23170=> 0.707 +0.707 *
i
real14 <= real15 + mr14; -- + xr32138 - xi6393=> 0.981 +0.195 *
i
real15 <= real16 - mr15; -- + xr32768=> 1.000 -0.000 * i
real16 <= real17 + mr16; -- + xr32138 - xi6393=> 0.981 +0.195 *
i
real17 <= real18 + mr17; -- + xr23170 - xi23170=> 0.707 +0.707 *
i
real18 <= real19 + mr18; -- - xr6393 - xi32138=> -0.195 +0.981 *
i
real19 <= real20 + mr19; -- - xr32768=> -1.000 +0.000 * i
real20 <= real21 - mr20; -- + xr6393 + xi32138=> 0.195 -0.981 *
i
real21 <= real22 + mr21; -- + xr23170 - xi23170=> 0.707 +0.707 *
i
real22 <= real23 - mr22; -- - xr32138 + xi6393=> -0.981 -0.195 *
i
real23 <= real24 - mr23; -- + xr32768=> 1.000 -0.000 * i
real24 <= real25 - mr24; -- - xr32138 + xi6393=> -0.981 -0.195 *
i
real25 <= real26 + mr25; -- + xr23170 - xi23170=> 0.707 +0.707 *
i
real26 <= real27 - mr26; -- + xr6393 + xi32138=> 0.195 -0.981 *
i
real27 <= real28 + mr27; -- - xr32768=> -1.000 +0.000 * i
real28 <= real29 + mr28; -- - xr6393 - xi32138=> -0.195 +0.981 *
i
real29 <= real30 + mr29; -- + xr23170 - xi23170=> 0.707 +0.707 *
i
real30 <= mr30; -- xr32138 - xi6393;
-- Imaginary part of FIR filter in transposed form = xr*Coeff.i +
xi*Coeff.r
imag0 <= imag1 + mi0; -- + xr6393 + xi32138=> 0.981 +0.195 * i
imag1 <= imag2 + mi1; -- + xr23170 + xi23170=> 0.707 +0.707 * i
imag2 <= imag3 + mi2; -- + xr32138 - xi6393=> -0.195 +0.981 * i
imag3 <= imag4 + mi3; -- - xi32768=> -1.000 +0.000 * i
imag4 <= imag5 - mi4; -- - xr32138 + xi6393=> 0.195 -0.981 * i
imag5 <= imag6 + mi5; -- + xr23170 + xi23170=> 0.707 +0.707 * i
imag6 <= imag7 - mi6; -- - xr6393 - xi32138=> -0.981 -0.195 * i
imag7 <= imag8 - mi7; -- + xi32768=> 1.000 -0.000 * i
imag8 <= imag9 - mi8; -- - xr6393 - xi32138=> -0.981 -0.195 * i
imag9 <= imag10 + mi9; -- + xr23170 + xi23170=> 0.707 +0.707 * i
imag10 <= imag11 - mi10; -- - xr32138 + xi6393=> 0.195 -0.981 * i
imag11 <= imag12 + mi11; -- - xi32768=> -1.000 +0.000 * i
imag12 <= imag13 + mi12; -- + xr32138 - xi6393=> -0.195 +0.981 *
i
imag13 <= imag14 + mi13; -- + xr23170 + xi23170=> 0.707 +0.707 *
i
imag14 <= imag15 + mi14; -- + xr6393 + xi32138=> 0.981 +0.195 * i
imag15 <= imag16 - mi15; -- + xi32768=> 1.000 -0.000 * i
imag16 <= imag17 + mi16; -- + xr6393 + xi32138=> 0.981 +0.195 * i
imag17 <= imag18 + mi17; -- + xr23170 + xi23170=> 0.707 +0.707 *
i
imag18 <= imag19 + mi18; -- + xr32138 - xi6393=> -0.195 +0.981 *
i
imag19 <= imag20 + mi19; -- - xi32768=> -1.000 +0.000 * i
imag20 <= imag21 - mi20; -- - xr32138 + xi6393=> 0.195 -0.981 * i
imag21 <= imag22 + mi21; -- + xr23170 + xi23170=> 0.707 +0.707 *
i
imag22 <= imag23 - mi22; -- - xr6393 - xi32138=> -0.981 -0.195 *
i
imag23 <= imag24 - mi23; -- + xi32768=> 1.000 -0.000 * i
imag24 <= imag25 - mi24; -- - xr6393 - xi32138=> -0.981 -0.195 *
i
imag25 <= imag26 + mi25; -- + xr23170 + xi23170=> 0.707 +0.707 *
i
imag26 <= imag27 - mi26; -- - xr32138 + xi6393=> 0.195 -0.981 * i
imag27 <= imag28 + mi27; -- - xi32768=> -1.000 +0.000 * i
imag28 <= imag29 + mi28; -- + xr32138 - xi6393=> -0.195 +0.981 *
i
imag29 <= imag30 + mi29; -- + xr23170 + xi23170=> 0.707 +0.707 *
i
imag30 <= mi30; -- xr6393 + xi32138;
END PROCESS Structure;
-- Use table to get INPUT (=OUTPUT!) twiddle factor coefficients
tab_1: d16b16
PORT MAP( t_in => t1_in,
re_out => t1_real,
im_out => t1_imag);
t1_real_out <= t1_real;
t1_imag_out <= t1_imag;
-- Multiply inputs with twiddle factor exp(j*phi)
ccmul_1: cmi3a5b16
PORT MAP (clk => clk, -- Clock for the output register
x_in => x_real, y_in => x_imag,
c_in => t1_real, s_in => t1_imag,
r_out => ccmul_r , i_out => ccmul_i);
ccmul_r_out <= ccmul_r;
ccmul_i_out <= ccmul_i;
-- Multiplex for the complex multiplier inputs
-- Use DFT input for the first N steps and than the filter outputs
--MPX: PROCESS (x_real, x_imag, r0, i0)
--BEGIN
--IF count < 17 THEN
-- real_in <= x_real_in;
-- imag_in <= x_imag_in;
--ELSE
-- real_in <= r0;
-- imag_in <= i0;
--END IF;
--END PROCESS MPX;
-- Sign extentsion for the multiplier output, i.e. filter input
Sxt: PROCESS (ccmul_r, ccmul_i)
BEGIN
IF count <= 17 THEN
sxtxr(W-1 DOWNTO 0) <= ccmul_r;
sxtxi(W-1 DOWNTO 0) <= ccmul_i;
FOR k IN Wfir-1 DOWNTO W LOOP
sxtxr(k) <= ccmul_r(ccmul_r'left);
sxtxi(k) <= ccmul_i(ccmul_i'left);
END LOOP;
ELSE
sxtxr <= (OTHERS => '0');
sxtxi <= (OTHERS => '0');
END IF;
END PROCESS Sxt;
sxtxr_out <= sxtxr;
sxtxi_out <= sxtxi;
-- Multiply filter output with twiddle factor exp(j*phi)
tab_2: d16b16
PORT MAP(t_in=>t2_in,
re_out=>t2_real,
im_out=>t2_imag);
t2_real_out<=t2_real;
t2_imag_out<=t2_imag;
r0 <= CONV_STD_LOGIC_VECTOR( real0 / 16, 16);
i0 <= CONV_STD_LOGIC_VECTOR( imag0 / 16, 16);
r0_out <= r0;
i0_out <= i0;
ccmul_2: cmi3a5b16
PORT MAP (clk => clk, -- Clock for the output register
x_in => r0, y_in => i0,
c_in => t2_real, s_in => t2_imag,
r_out => y_r , i_out => y_i);
END flex;
------------------------------------------------------------------------------
--- Multiplier---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cmi3a5b16 is
GENERIC (W2 : INTEGER := 33; -- Multiplier bit width
W1 : INTEGER := 17; -- Bit width c+s sum
W : INTEGER := 16); -- Input bit width
Port ( clk : in std_logic;
x_in : in std_logic_vector(W-1 downto 0);
y_in : in std_logic_vector(W-1 downto 0);
s_in : in std_logic_vector(W-1 downto 0);
c_in : in std_logic_vector(W-1 downto 0);
r_out,i_out: out std_logic_vector(W-1 downto 0));
end cmi3a5b16;
architecture Behavioral of cmi3a5b16 is
signal x,y,c,s:std_logic_vector (W-1 downto 0);
signal sxtx,sxty,xmy,cps,cms:std_logic_vector(W1-1 downto 0);
signal xmyc,cpsx,cmsy,r,i:std_logic_vector(W2-1 downto 0);
begin
p1
rocess--(x_in,y_in,c_in,s_in)
begin
wait until clk='1';
x<=x_in;
y<=y_in;
c<=c_in;
s<=s_in;
cps<=(c_in(c_in'left)&c_in) + (s_in(s_in'left)&s_in);
cms<=(c_in(c_in'left)&c_in)-(s_in(s_in'left)&s_in);
END PROCESS p1;
sxtx<=x(x'left)&x;
sxty<=y(y'left)&y;
xmy<=sxtx-sxty;
xmyc<=xmy*c;
cmsy<=cms*y;
cpsx<=cps*x;
r<=cmsy+xmyc;
i<=cpsx-xmyc;
p2rocess(r,i)
begin
r_out<=r(W2-3 downto W-1);
i_out<=i(W2-3 downto W-1);
end process p2;
end Behavioral;
--------------------------------------------------
--- Twiddle factors
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_signed.ALL;
ENTITY d16b16 IS
PORT ( t_in : IN STD_LOGIC_VECTOR(4-1 DOWNTO 0);
-- clk : IN STD_LOGIC;
re_out : OUT STD_LOGIC_VECTOR(16-1 DOWNTO 0);
im_out : OUT STD_LOGIC_VECTOR(16-1 DOWNTO 0));
END d16b16;
ARCHITECTURE LCs OF d16b16 IS
BEGIN
-- This is the 16 bit (i.e. -32767 ... 32767) CASE table for
-- the 16-point CZT pre- and post-multiplications
-- automatic generated with cztgen.exe -- DO NOT EDIT!
-- Table implements the mapping
PROCESS(t_in)
-- VARIABLE t_in : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
BEGIN
-- WAIT UNTIL clk = '1'; -- For benchmark only
-- CASE table_in IS
CASE t_in IS -- For benchmark only
WHEN "0000" => re_out <= "0111111111111111"; -- = 32767
i.e. 1.000
im_out <= "0000000000000000"; -- = 0 i.e.
0.000
WHEN "0001" => re_out <= "0111110110001001"; -- = 32137
i.e. 0.981
im_out <= "1110011100000111"; -- = -6393
i.e. -0.195
WHEN "0010" => re_out <= "0101101010000010"; -- = 23170
i.e. 0.707
im_out <= "1010010101111110"; -- = -23170
i.e. -0.707
WHEN "0011" => re_out <= "1110011100000111"; -- = -6393
i.e. -0.195
im_out <= "1000001001110111"; -- = -32137
i.e. -0.981
WHEN "0100" => re_out <= "1000000000000001"; -- = -32767
i.e. -1.000
im_out <= "0000000000000000"; -- = 0 i.e.
-0.000
WHEN "0101" => re_out <= "0001100011111001"; -- = 6393 i.e.
0.195
im_out <= "0111110110001001"; -- = 32137
i.e. 0.981
WHEN "0110" => re_out <= "0101101010000010"; -- = 23170
i.e. 0.707
im_out <= "1010010101111110"; -- = -23170
i.e. -0.707
WHEN "0111" => re_out <= "1000001001110111"; -- = -32137
i.e. -0.981
im_out <= "0001100011111001"; -- = 6393 i.e.
0.195
WHEN "1000" => re_out <= "0111111111111111"; -- = 32767
i.e. 1.000
im_out <= "0000000000000000"; -- = 0 i.e.
0.000
WHEN "1001" => re_out <= "1000001001110111"; -- = -32137
i.e. -0.981
im_out <= "0001100011111001"; -- = 6393 i.e.
0.195
WHEN "1010" => re_out <= "0101101010000010"; -- = 23170
i.e. 0.707
im_out <= "1010010101111110"; -- = -23170
i.e. -0.707
WHEN "1011" => re_out <= "0001100011111001"; -- = 6393 i.e.
0.195
im_out <= "0111110110001001"; -- = 32137
i.e. 0.981
WHEN "1100" => re_out <= "1000000000000001"; -- = -32767
i.e. -1.000
im_out <= "0000000000000000"; -- = 0 i.e.
-0.000
WHEN "1101" => re_out <= "1110011100000111"; -- = -6393
i.e. -0.195
im_out <= "1000001001110111"; -- = -32137
i.e. -0.981
WHEN "1110" => re_out <= "0101101010000010"; -- = 23170
i.e. 0.707
im_out <= "1010010101111110"; -- = -23170
i.e. -0.707
WHEN "1111" => re_out <= "0111110110001001"; -- = 32137
i.e. 0.981
im_out <= "1110011100000111"; -- = -6393
i.e. -0.195
WHEN OTHERS => re_out <= (OTHERS => '0');
im_out <= (OTHERS => '0');
END CASE;
-- t_in := table_in; -- For benchmark only
END PROCESS;
END LCs;
-------------------------------------------------------------------------
I have an automatically generated code from some source
"cztgen.exe". I am working on performing FFT (C-Z Tfranform).The code
basically has filter (FIR)coefficient computation and convolution .I
am using two other
code to perform multiplication and
store coefficient/twiddle factors(not that of filter). My problem is I
am not getting write answers when i simulate the codes.The multiplier
and coefficent(not that of filter) codes are working fine. When put
together, I don't get right answer. I suspect there is some problem
with the filter coefficent code.
How do I check the code? and where can I find the source for the
filter coeff. code.Thank you.
Hari
PS: here's the code for reference.
-- This is the 16-point CZT FSM and FIR filter
-- automatic generated with cztgen.exe -- DO NOT EDIT!
-- The filter has 4 real and 4 imaginary different coefficients
-- Coefficient bits = 16 Data bits = 16
-- OVL guard bits = 0 LSB guard bits = 4
-- Scale Multiplier = 2048 Scale FIR = 16
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_signed.ALL;
ENTITY czr16s16o0g4h IS ------> Interface
GENERIC (Wfir: INTEGER := 20; -- Filter accu bit width
Lfir: INTEGER := 31; -- Filter length = 2*DFTlenght-1
W1 : INTEGER := 4; -- log2(DFT length)
W : INTEGER := 16); -- Data/Coeff bit width
PORT ( clk : IN STD_LOGIC;
x_real_in, x_imag_in : IN STD_LOGIC_VECTOR(W-1 DOWNTO 0);
valid_in : OUT STD_LOGIC;
t1_real_out,t1_imag_out, ccmul_r_out,t2_real_out,t2_imag_out,
ccmul_i_out : OUT STD_LOGIC_VECTOR(W-1 DOWNTO 0);
countn : OUT integer range 0 to 100;
r0_out, i0_out : OUT STD_LOGIC_VECTOR(W-1 DOWNTO 0);
sxtxr_out, sxtxi_out : OUT STD_LOGIC_VECTOR(Wfir-1 DOWNTO 0);
valid_out : OUT STD_LOGIC;
y_real, y_imag : OUT STD_LOGIC_VECTOR(W-1 DOWNTO 0));
END czr16s16o0g4h;
ARCHITECTURE flex OF czr16s16o0g4h IS
COMPONENT d16b16
PORT ( t_in : IN STD_LOGIC_VECTOR(4-1 DOWNTO 0);
re_out : OUT STD_LOGIC_VECTOR(16-1 DOWNTO 0);
im_out : OUT STD_LOGIC_VECTOR(16-1 DOWNTO 0));
END COMPONENT;
COMPONENT cmi3a5b16
GENERIC (W2 : INTEGER := 33; -- Multiplier bit width
W1 : INTEGER := 17; -- Bit width c+s sum
W : INTEGER := 16); -- Input bit width
PORT (clk : STD_LOGIC; -- Clock for the output register
x_in, y_in : IN STD_LOGIC_VECTOR(W-1 DOWNTO 0);
c_in, s_in : IN STD_LOGIC_VECTOR(W-1 DOWNTO 0);
r_out, i_out : OUT STD_LOGIC_VECTOR(W-1 DOWNTO 0));
END COMPONENT;
SIGNAL count : integer RANGE 0 TO 63;
TYPE STATE_TYPE IS (Start, Load, Run);
SIGNAL state : STATE_TYPE ;
SIGNAL x_real, x_imag : STD_LOGIC_VECTOR(W-1 DOWNTO 0);
SUBTYPE WORD IS INTEGER;-- RANGE -2**19 TO 2**19-1;
SIGNAL mr0, mi0, real0, imag0 : WORD; -- Tapped delay line
SIGNAL mr1, mi1, real1, imag1 : WORD; -- Tapped delay line
SIGNAL mr2, mi2, real2, imag2 : WORD; -- Tapped delay line
SIGNAL mr3, mi3, real3, imag3 : WORD; -- Tapped delay line
SIGNAL mr4, mi4, real4, imag4 : WORD; -- Tapped delay line
SIGNAL mr5, mi5, real5, imag5 : WORD; -- Tapped delay line
SIGNAL mr6, mi6, real6, imag6 : WORD; -- Tapped delay line
SIGNAL mr7, mi7, real7, imag7 : WORD; -- Tapped delay line
SIGNAL mr8, mi8, real8, imag8 : WORD; -- Tapped delay line
SIGNAL mr9, mi9, real9, imag9 : WORD; -- Tapped delay line
SIGNAL mr10, mi10, real10, imag10 : WORD; -- Tapped delay line
SIGNAL mr11, mi11, real11, imag11 : WORD; -- Tapped delay line
SIGNAL mr12, mi12, real12, imag12 : WORD; -- Tapped delay line
SIGNAL mr13, mi13, real13, imag13 : WORD; -- Tapped delay line
SIGNAL mr14, mi14, real14, imag14 : WORD; -- Tapped delay line
SIGNAL mr15, mi15, real15, imag15 : WORD; -- Tapped delay line
SIGNAL mr16, mi16, real16, imag16 : WORD; -- Tapped delay line
SIGNAL mr17, mi17, real17, imag17 : WORD; -- Tapped delay line
SIGNAL mr18, mi18, real18, imag18 : WORD; -- Tapped delay line
SIGNAL mr19, mi19, real19, imag19 : WORD; -- Tapped delay line
SIGNAL mr20, mi20, real20, imag20 : WORD; -- Tapped delay line
SIGNAL mr21, mi21, real21, imag21 : WORD; -- Tapped delay line
SIGNAL mr22, mi22, real22, imag22 : WORD; -- Tapped delay line
SIGNAL mr23, mi23, real23, imag23 : WORD; -- Tapped delay line
SIGNAL mr24, mi24, real24, imag24 : WORD; -- Tapped delay line
SIGNAL mr25, mi25, real25, imag25 : WORD; -- Tapped delay line
SIGNAL mr26, mi26, real26, imag26 : WORD; -- Tapped delay line
SIGNAL mr27, mi27, real27, imag27 : WORD; -- Tapped delay line
SIGNAL mr28, mi28, real28, imag28 : WORD; -- Tapped delay line
SIGNAL mr29, mi29, real29, imag29 : WORD; -- Tapped delay line
SIGNAL mr30, mi30, real30, imag30 : WORD; -- Tapped delay line
-----******** Real and imaginary filter coefficients computed with
RAG:
SIGNAL xr1, xi1 : WORD;
SIGNAL xr31, xi31 : WORD;
SIGNAL xr97, xi97 : WORD;
SIGNAL xr125, xi125 : WORD;
SIGNAL xr251, xi251 : WORD;
SIGNAL xr399, xi399 : WORD;
SIGNAL xr799, xi799 : WORD;
SIGNAL xr4017, xi4017 : WORD;
SIGNAL xr6393, xi6393 : WORD;
SIGNAL xr11585, xi11585 : WORD;
SIGNAL xr11973, xi11973 : WORD;
SIGNAL xr16069, xi16069 : WORD;
SIGNAL xr23170, xi23170 : WORD;
SIGNAL xr32138, xi32138 : WORD;
SIGNAL xr32768, xi32768 : WORD;
-- Auxiliary signal definitions
SIGNAL t1_in,t2_in :
STD_LOGIC_VECTOR(W1-1 DOWNTO 0);
SIGNAL real_in, imag_in : STD_LOGIC_VECTOR(W-1
DOWNTO 0);
SIGNAL t1_real, t1_imag,t2_real,t2_imag : STD_LOGIC_VECTOR(W-1
DOWNTO 0);
SIGNAL ccmul_r, ccmul_i : STD_LOGIC_VECTOR(W-1
DOWNTO 0);
SIGNAL sxtxr, sxtxi : STD_LOGIC_VECTOR(Wfir-1
DOWNTO 0);
SIGNAL r0, i0 : STD_LOGIC_VECTOR(W-1
DOWNTO 0);
SIGNAL y_r, y_i : STD_LOGIC_VECTOR(W-1
DOWNTO 0);
BEGIN
States: PROCESS ------> State machine for CZT filter
BEGIN
WAIT UNTIL clk = '1';
CASE state IS
WHEN Start => -- Initialization step
state <= Load;
count <= 0;
t1_in <= "0000"; -- Reset tables
t2_in <= "0000";
WHEN Load => -- Multiply inputs with twiddle factors
IF count = 17 THEN -- Load phase done ?
state <= Run;
ELSE
state <= Load;
t1_in <= t1_in + "0001";
END IF;
-- IF count < 16 THEN
-- t1_in<=t1_in+"0001";
-- ELSE
-- t1_in<="0000";
-- END IF;
count<=count+1;
countn<=count;
WHEN Run => -- Multiply filter output with twiddle factors
IF count = 47 THEN -- Run phase done ?
state <= Start; -- Output of result
t1_in <= "0000"; -- Reset tables
ELSE -- and start again
state <= Run;
t2_in <= t2_in + "0001";
END IF;
count<=count+1;
countn<=count;
IF count > 19 AND count < 36 THEN
valid_out <= '1';
y_real <= y_r;--ccmul_r;
y_imag <= y_i;--ccmul_i;
ELSE
valid_out <= '0';
y_real <= (OTHERS => '0');
y_imag <= (OTHERS => '0');
END IF;
IF count < 15 THEN
valid_in <= '1';
ELSE
valid_in <= '0';
END IF;
END CASE;
END PROCESS States;
-- Note that all signals: xrXXX, xiXXX are global defined
Coeffs: PROCESS (sxtxr, sxtxi)
VARIABLE xr, xi : WORD;
BEGIN
-- Compute the filter coefficients but use no FFs
xr := CONV_INTEGER(sxtxr);
xi := CONV_INTEGER(sxtxi);
-- rag: Generate even coefficients by shift of fundamentals
xr1 <= xr;
xi1 <= xi;
xr32138 <= xr16069 * 2 / 2048;
xi32138 <= xi16069 * 2 / 2048;
xr23170 <= xr11585 * 2 / 2048;
xi23170 <= xi11585 * 2 / 2048;
xr32768 <= xr1 * 32768 / 2048;
xi32768 <= xi1 * 32768 / 2048;
-- rag: Generate coefficient by mutiplying fundamentals with
power-of-2
xr31 <= xr1 * 32 - xr1 * 1;
xi31 <= xi1 * 32 - xi1 * 1;
xr125 <= xr31 * 4 + xr1 * 1;
xi125 <= xi31 * 4 + xi1 * 1;
xr251 <= xr125 * 2 + xr1 * 1;
xi251 <= xi125 * 2 + xi1 * 1;
xr4017 <= xr251 * 16 + xr1 * 1;
xi4017 <= xi251 * 16 + xi1 * 1;
xr16069 <= xr4017 * 4 + xr1 * 1;
xi16069 <= xi4017 * 4 + xi1 * 1;
xr97 <= xr1 * 128 - xr31 * 1;
xi97 <= xi1 * 128 - xi31 * 1;
xr11973 <= xr16069 * 1 - xr1 * 4096;
xi11973 <= xi16069 * 1 - xi1 * 4096;
xr11585 <= xr11973 * 1 - xr97 * 4;
xi11585 <= xi11973 * 1 - xi97 * 4;
xr399 <= xr31 * 16 - xr97 * 1;
xi399 <= xi31 * 16 - xi97 * 1;
xr799 <= xr399 * 2 + xr1 * 1;
xi799 <= xi399 * 2 + xi1 * 1;
xr6393 <= (xr799 * 8 + xr1 * 1) / 2048;
xi6393 <= (xi799 * 8 + xi1 * 1) / 2048;
-- Comp. Time= 12.000000 sec.
-- Results adder: rag = 22 mag = 20 csd = 26
-- Resources: length extfund = 91 summat = 6546
-- RAG with Add/Sub
-- linput= 4 lcoefft = 3 mag table used = 18 bits
END PROCESS Coeffs;
-- Real and imaginary complex filter coefficients
-- Real part = xr*Coeff.r - xi*Coeff.i
-- Imaginary part = xr*Coeff.i + xi*Coeff.r
Cmuls: PROCESS ( xr32138, xr6393, xr23170, xr32768,
xi32138 ,xi6393 ,xi23170 ,xi32768)
BEGIN -- filters in transposed form
-- WAIT UNTIL clk = '1';
-- no FF for input signals
mr0 <= xr32138 - xi6393; -- sign = +
mi0 <= xr6393 + xi32138; -- = 0.981 +0.195 * i
mr1 <= xr23170 - xi23170; -- sign = +
mi1 <= xr23170 + xi23170; -- = 0.707 +0.707 * i
mr2 <= - xr6393 - xi32138; -- sign = +
mi2 <= xr32138 - xi6393; -- = -0.195 +0.981 * i
mr3 <= - xr32768; -- sign = +
mi3 <= - xi32768; -- = -1.000 +0.000 * i
mr4 <= mr2; -- sign = -
mi4 <= mi2; -- = 0.195 -0.981 * i
mr5 <= mr1; -- sign = +
mi5 <= mi1; -- = 0.707 +0.707 * i
mr6 <= mr0; -- sign = -
mi6 <= mi0; -- = -0.981 -0.195 * i
mr7 <= mr3; -- sign = -
mi7 <= mi3; -- = 1.000 -0.000 * i
mr8 <= mr0; -- sign = -
mi8 <= mi0; -- = -0.981 -0.195 * i
mr9 <= mr1; -- sign = +
mi9 <= mi1; -- = 0.707 +0.707 * i
mr10 <= mr2; -- sign = -
mi10 <= mi2; -- = 0.195 -0.981 * i
mr11 <= mr3; -- sign = +
mi11 <= mi3; -- = -1.000 +0.000 * i
mr12 <= mr2; -- sign = +
mi12 <= mi2; -- = -0.195 +0.981 * i
mr13 <= mr1; -- sign = +
mi13 <= mi1; -- = 0.707 +0.707 * i
mr14 <= mr0; -- sign = +
mi14 <= mi0; -- = 0.981 +0.195 * i
mr15 <= mr3; -- sign = -
mi15 <= mi3; -- = 1.000 -0.000 * i
mr16 <= mr0; -- sign = +
mi16 <= mi0; -- = 0.981 +0.195 * i
mr17 <= mr1; -- sign = +
mi17 <= mi1; -- = 0.707 +0.707 * i
mr18 <= mr2; -- sign = +
mi18 <= mi2; -- = -0.195 +0.981 * i
mr19 <= mr3; -- sign = +
mi19 <= mi3; -- = -1.000 +0.000 * i
mr20 <= mr2; -- sign = -
mi20 <= mi2; -- = 0.195 -0.981 * i
mr21 <= mr1; -- sign = +
mi21 <= mi1; -- = 0.707 +0.707 * i
mr22 <= mr0; -- sign = -
mi22 <= mi0; -- = -0.981 -0.195 * i
mr23 <= mr3; -- sign = -
mi23 <= mi3; -- = 1.000 -0.000 * i
mr24 <= mr0; -- sign = -
mi24 <= mi0; -- = -0.981 -0.195 * i
mr25 <= mr1; -- sign = +
mi25 <= mi1; -- = 0.707 +0.707 * i
mr26 <= mr2; -- sign = -
mi26 <= mi2; -- = 0.195 -0.981 * i
mr27 <= mr3; -- sign = +
mi27 <= mi3; -- = -1.000 +0.000 * i
mr28 <= mr2; -- sign = +
mi28 <= mi2; -- = -0.195 +0.981 * i
mr29 <= mr1; -- sign = +
mi29 <= mi1; -- = 0.707 +0.707 * i
mr30 <= mr0; -- sign = +
mi30 <= mi0; -- = 0.981 +0.195 * i
END PROCESS Cmuls;
Structure: PROCESS --(mr0,mr1,mr2,mr3,mr4,mr5,mr6,mr7,mr8,mr9,mr10,
--
mr11,mr12,mr13,mr14,mr15,mr16,mr17,mr18,mr19,mr20,mr20,mr21,mr22,mr23,
--mr24,mr25,mr26,mr27,mr28,mr29,mr30,mi0,mi1,mi2,mi3,mi4,mi5,mi6,mi7,mi8,
--mi9,mi10,mi11,mi12,mi13,mi14,mi15,mi16,mi17,mi18,mi19,mi20,mi21,mi22,mi23,
--mi24,mi25,mi26,mi27,mi28,mi29,mi30) -- Structure of the two
FIR
BEGIN -- filters in transposed form
WAIT UNTIL clk = '1';
-- FF for input signals
x_real <= x_real_in;
x_imag <= x_imag_in;
-- Real part of FIR filter in transposed form = xr*Coeff.r -
xi*Coeff.i
real0 <= real1 + mr0; -- + xr32138 - xi6393=> 0.981 +0.195 * i
real1 <= real2 + mr1; -- + xr23170 - xi23170=> 0.707 +0.707 * i
real2 <= real3 + mr2; -- - xr6393 - xi32138=> -0.195 +0.981 * i
real3 <= real4 + mr3; -- - xr32768=> -1.000 +0.000 * i
real4 <= real5 - mr4; -- + xr6393 + xi32138=> 0.195 -0.981 * i
real5 <= real6 + mr5; -- + xr23170 - xi23170=> 0.707 +0.707 * i
real6 <= real7 - mr6; -- - xr32138 + xi6393=> -0.981 -0.195 * i
real7 <= real8 - mr7; -- + xr32768=> 1.000 -0.000 * i
real8 <= real9 - mr8; -- - xr32138 + xi6393=> -0.981 -0.195 * i
real9 <= real10 + mr9; -- + xr23170 - xi23170=> 0.707 +0.707 * i
real10 <= real11 - mr10; -- + xr6393 + xi32138=> 0.195 -0.981 *
i
real11 <= real12 + mr11; -- - xr32768=> -1.000 +0.000 * i
real12 <= real13 + mr12; -- - xr6393 - xi32138=> -0.195 +0.981 *
i
real13 <= real14 + mr13; -- + xr23170 - xi23170=> 0.707 +0.707 *
i
real14 <= real15 + mr14; -- + xr32138 - xi6393=> 0.981 +0.195 *
i
real15 <= real16 - mr15; -- + xr32768=> 1.000 -0.000 * i
real16 <= real17 + mr16; -- + xr32138 - xi6393=> 0.981 +0.195 *
i
real17 <= real18 + mr17; -- + xr23170 - xi23170=> 0.707 +0.707 *
i
real18 <= real19 + mr18; -- - xr6393 - xi32138=> -0.195 +0.981 *
i
real19 <= real20 + mr19; -- - xr32768=> -1.000 +0.000 * i
real20 <= real21 - mr20; -- + xr6393 + xi32138=> 0.195 -0.981 *
i
real21 <= real22 + mr21; -- + xr23170 - xi23170=> 0.707 +0.707 *
i
real22 <= real23 - mr22; -- - xr32138 + xi6393=> -0.981 -0.195 *
i
real23 <= real24 - mr23; -- + xr32768=> 1.000 -0.000 * i
real24 <= real25 - mr24; -- - xr32138 + xi6393=> -0.981 -0.195 *
i
real25 <= real26 + mr25; -- + xr23170 - xi23170=> 0.707 +0.707 *
i
real26 <= real27 - mr26; -- + xr6393 + xi32138=> 0.195 -0.981 *
i
real27 <= real28 + mr27; -- - xr32768=> -1.000 +0.000 * i
real28 <= real29 + mr28; -- - xr6393 - xi32138=> -0.195 +0.981 *
i
real29 <= real30 + mr29; -- + xr23170 - xi23170=> 0.707 +0.707 *
i
real30 <= mr30; -- xr32138 - xi6393;
-- Imaginary part of FIR filter in transposed form = xr*Coeff.i +
xi*Coeff.r
imag0 <= imag1 + mi0; -- + xr6393 + xi32138=> 0.981 +0.195 * i
imag1 <= imag2 + mi1; -- + xr23170 + xi23170=> 0.707 +0.707 * i
imag2 <= imag3 + mi2; -- + xr32138 - xi6393=> -0.195 +0.981 * i
imag3 <= imag4 + mi3; -- - xi32768=> -1.000 +0.000 * i
imag4 <= imag5 - mi4; -- - xr32138 + xi6393=> 0.195 -0.981 * i
imag5 <= imag6 + mi5; -- + xr23170 + xi23170=> 0.707 +0.707 * i
imag6 <= imag7 - mi6; -- - xr6393 - xi32138=> -0.981 -0.195 * i
imag7 <= imag8 - mi7; -- + xi32768=> 1.000 -0.000 * i
imag8 <= imag9 - mi8; -- - xr6393 - xi32138=> -0.981 -0.195 * i
imag9 <= imag10 + mi9; -- + xr23170 + xi23170=> 0.707 +0.707 * i
imag10 <= imag11 - mi10; -- - xr32138 + xi6393=> 0.195 -0.981 * i
imag11 <= imag12 + mi11; -- - xi32768=> -1.000 +0.000 * i
imag12 <= imag13 + mi12; -- + xr32138 - xi6393=> -0.195 +0.981 *
i
imag13 <= imag14 + mi13; -- + xr23170 + xi23170=> 0.707 +0.707 *
i
imag14 <= imag15 + mi14; -- + xr6393 + xi32138=> 0.981 +0.195 * i
imag15 <= imag16 - mi15; -- + xi32768=> 1.000 -0.000 * i
imag16 <= imag17 + mi16; -- + xr6393 + xi32138=> 0.981 +0.195 * i
imag17 <= imag18 + mi17; -- + xr23170 + xi23170=> 0.707 +0.707 *
i
imag18 <= imag19 + mi18; -- + xr32138 - xi6393=> -0.195 +0.981 *
i
imag19 <= imag20 + mi19; -- - xi32768=> -1.000 +0.000 * i
imag20 <= imag21 - mi20; -- - xr32138 + xi6393=> 0.195 -0.981 * i
imag21 <= imag22 + mi21; -- + xr23170 + xi23170=> 0.707 +0.707 *
i
imag22 <= imag23 - mi22; -- - xr6393 - xi32138=> -0.981 -0.195 *
i
imag23 <= imag24 - mi23; -- + xi32768=> 1.000 -0.000 * i
imag24 <= imag25 - mi24; -- - xr6393 - xi32138=> -0.981 -0.195 *
i
imag25 <= imag26 + mi25; -- + xr23170 + xi23170=> 0.707 +0.707 *
i
imag26 <= imag27 - mi26; -- - xr32138 + xi6393=> 0.195 -0.981 * i
imag27 <= imag28 + mi27; -- - xi32768=> -1.000 +0.000 * i
imag28 <= imag29 + mi28; -- + xr32138 - xi6393=> -0.195 +0.981 *
i
imag29 <= imag30 + mi29; -- + xr23170 + xi23170=> 0.707 +0.707 *
i
imag30 <= mi30; -- xr6393 + xi32138;
END PROCESS Structure;
-- Use table to get INPUT (=OUTPUT!) twiddle factor coefficients
tab_1: d16b16
PORT MAP( t_in => t1_in,
re_out => t1_real,
im_out => t1_imag);
t1_real_out <= t1_real;
t1_imag_out <= t1_imag;
-- Multiply inputs with twiddle factor exp(j*phi)
ccmul_1: cmi3a5b16
PORT MAP (clk => clk, -- Clock for the output register
x_in => x_real, y_in => x_imag,
c_in => t1_real, s_in => t1_imag,
r_out => ccmul_r , i_out => ccmul_i);
ccmul_r_out <= ccmul_r;
ccmul_i_out <= ccmul_i;
-- Multiplex for the complex multiplier inputs
-- Use DFT input for the first N steps and than the filter outputs
--MPX: PROCESS (x_real, x_imag, r0, i0)
--BEGIN
--IF count < 17 THEN
-- real_in <= x_real_in;
-- imag_in <= x_imag_in;
--ELSE
-- real_in <= r0;
-- imag_in <= i0;
--END IF;
--END PROCESS MPX;
-- Sign extentsion for the multiplier output, i.e. filter input
Sxt: PROCESS (ccmul_r, ccmul_i)
BEGIN
IF count <= 17 THEN
sxtxr(W-1 DOWNTO 0) <= ccmul_r;
sxtxi(W-1 DOWNTO 0) <= ccmul_i;
FOR k IN Wfir-1 DOWNTO W LOOP
sxtxr(k) <= ccmul_r(ccmul_r'left);
sxtxi(k) <= ccmul_i(ccmul_i'left);
END LOOP;
ELSE
sxtxr <= (OTHERS => '0');
sxtxi <= (OTHERS => '0');
END IF;
END PROCESS Sxt;
sxtxr_out <= sxtxr;
sxtxi_out <= sxtxi;
-- Multiply filter output with twiddle factor exp(j*phi)
tab_2: d16b16
PORT MAP(t_in=>t2_in,
re_out=>t2_real,
im_out=>t2_imag);
t2_real_out<=t2_real;
t2_imag_out<=t2_imag;
r0 <= CONV_STD_LOGIC_VECTOR( real0 / 16, 16);
i0 <= CONV_STD_LOGIC_VECTOR( imag0 / 16, 16);
r0_out <= r0;
i0_out <= i0;
ccmul_2: cmi3a5b16
PORT MAP (clk => clk, -- Clock for the output register
x_in => r0, y_in => i0,
c_in => t2_real, s_in => t2_imag,
r_out => y_r , i_out => y_i);
END flex;
------------------------------------------------------------------------------
--- Multiplier---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cmi3a5b16 is
GENERIC (W2 : INTEGER := 33; -- Multiplier bit width
W1 : INTEGER := 17; -- Bit width c+s sum
W : INTEGER := 16); -- Input bit width
Port ( clk : in std_logic;
x_in : in std_logic_vector(W-1 downto 0);
y_in : in std_logic_vector(W-1 downto 0);
s_in : in std_logic_vector(W-1 downto 0);
c_in : in std_logic_vector(W-1 downto 0);
r_out,i_out: out std_logic_vector(W-1 downto 0));
end cmi3a5b16;
architecture Behavioral of cmi3a5b16 is
signal x,y,c,s:std_logic_vector (W-1 downto 0);
signal sxtx,sxty,xmy,cps,cms:std_logic_vector(W1-1 downto 0);
signal xmyc,cpsx,cmsy,r,i:std_logic_vector(W2-1 downto 0);
begin
p1
rocess--(x_in,y_in,c_in,s_in)begin
wait until clk='1';
x<=x_in;
y<=y_in;
c<=c_in;
s<=s_in;
cps<=(c_in(c_in'left)&c_in) + (s_in(s_in'left)&s_in);
cms<=(c_in(c_in'left)&c_in)-(s_in(s_in'left)&s_in);
END PROCESS p1;
sxtx<=x(x'left)&x;
sxty<=y(y'left)&y;
xmy<=sxtx-sxty;
xmyc<=xmy*c;
cmsy<=cms*y;
cpsx<=cps*x;
r<=cmsy+xmyc;
i<=cpsx-xmyc;
p2
rocess(r,i)begin
r_out<=r(W2-3 downto W-1);
i_out<=i(W2-3 downto W-1);
end process p2;
end Behavioral;
--------------------------------------------------
--- Twiddle factors
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_signed.ALL;
ENTITY d16b16 IS
PORT ( t_in : IN STD_LOGIC_VECTOR(4-1 DOWNTO 0);
-- clk : IN STD_LOGIC;
re_out : OUT STD_LOGIC_VECTOR(16-1 DOWNTO 0);
im_out : OUT STD_LOGIC_VECTOR(16-1 DOWNTO 0));
END d16b16;
ARCHITECTURE LCs OF d16b16 IS
BEGIN
-- This is the 16 bit (i.e. -32767 ... 32767) CASE table for
-- the 16-point CZT pre- and post-multiplications
-- automatic generated with cztgen.exe -- DO NOT EDIT!
-- Table implements the mapping
PROCESS(t_in)
-- VARIABLE t_in : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
BEGIN
-- WAIT UNTIL clk = '1'; -- For benchmark only
-- CASE table_in IS
CASE t_in IS -- For benchmark only
WHEN "0000" => re_out <= "0111111111111111"; -- = 32767
i.e. 1.000
im_out <= "0000000000000000"; -- = 0 i.e.
0.000
WHEN "0001" => re_out <= "0111110110001001"; -- = 32137
i.e. 0.981
im_out <= "1110011100000111"; -- = -6393
i.e. -0.195
WHEN "0010" => re_out <= "0101101010000010"; -- = 23170
i.e. 0.707
im_out <= "1010010101111110"; -- = -23170
i.e. -0.707
WHEN "0011" => re_out <= "1110011100000111"; -- = -6393
i.e. -0.195
im_out <= "1000001001110111"; -- = -32137
i.e. -0.981
WHEN "0100" => re_out <= "1000000000000001"; -- = -32767
i.e. -1.000
im_out <= "0000000000000000"; -- = 0 i.e.
-0.000
WHEN "0101" => re_out <= "0001100011111001"; -- = 6393 i.e.
0.195
im_out <= "0111110110001001"; -- = 32137
i.e. 0.981
WHEN "0110" => re_out <= "0101101010000010"; -- = 23170
i.e. 0.707
im_out <= "1010010101111110"; -- = -23170
i.e. -0.707
WHEN "0111" => re_out <= "1000001001110111"; -- = -32137
i.e. -0.981
im_out <= "0001100011111001"; -- = 6393 i.e.
0.195
WHEN "1000" => re_out <= "0111111111111111"; -- = 32767
i.e. 1.000
im_out <= "0000000000000000"; -- = 0 i.e.
0.000
WHEN "1001" => re_out <= "1000001001110111"; -- = -32137
i.e. -0.981
im_out <= "0001100011111001"; -- = 6393 i.e.
0.195
WHEN "1010" => re_out <= "0101101010000010"; -- = 23170
i.e. 0.707
im_out <= "1010010101111110"; -- = -23170
i.e. -0.707
WHEN "1011" => re_out <= "0001100011111001"; -- = 6393 i.e.
0.195
im_out <= "0111110110001001"; -- = 32137
i.e. 0.981
WHEN "1100" => re_out <= "1000000000000001"; -- = -32767
i.e. -1.000
im_out <= "0000000000000000"; -- = 0 i.e.
-0.000
WHEN "1101" => re_out <= "1110011100000111"; -- = -6393
i.e. -0.195
im_out <= "1000001001110111"; -- = -32137
i.e. -0.981
WHEN "1110" => re_out <= "0101101010000010"; -- = 23170
i.e. 0.707
im_out <= "1010010101111110"; -- = -23170
i.e. -0.707
WHEN "1111" => re_out <= "0111110110001001"; -- = 32137
i.e. 0.981
im_out <= "1110011100000111"; -- = -6393
i.e. -0.195
WHEN OTHERS => re_out <= (OTHERS => '0');
im_out <= (OTHERS => '0');
END CASE;
-- t_in := table_in; -- For benchmark only
END PROCESS;
END LCs;
-------------------------------------------------------------------------