FF array, is it a valid way to write it?

M

MM

Guest
Hi all,

Is the code below valid (including for synthesis)?


signal clk : std_logic_vector(0 to 3);

PROC:
process (clk)
begin
LP1:
for i in 0 to NUM loop
if clk(i)'event and clk(i)='0' then
queue(i) <= ldata(i);
end if;
end loop;
end process;

Thanks,
/Mikhail
 
No.

You need to create a component model for the ff and then use a for-generate
statement loop that instantiates and connects them together.



"MM" <mbmsv@yahoo.com> wrote in message
news:2jgpihF11ck8aU1@uni-berlin.de...
Hi all,

Is the code below valid (including for synthesis)?


signal clk : std_logic_vector(0 to 3);

PROC:
process (clk)
begin
LP1:
for i in 0 to NUM loop
if clk(i)'event and clk(i)='0' then
queue(i) <= ldata(i);
end if;
end loop;
end process;

Thanks,
/Mikhail
Click to expand...
 
JJ wrote:

You need to create a component model for the ff and then use a for-generate
statement loop that instantiates and connects them together.
Click to expand...
Could anybody tell me, why:


signal clk : std_logic_vector(0 to 3);

gen_gueues : for i in 0 to NUM generate
process (clk)
begin
if clk(i)'event and clk(i)='0' then
queue(i) <= ldata(i);
end if;
end process;
end generate;


is not allowed? This works in Cadence Leapfrog for simulation, but
Synopys Design Analyzer gives an error during synthesis.


Ralf
 
Ralf Hildebrandt <Ralf-Hildebrandt@gmx.de> writes:

JJ wrote:

You need to create a component model for the ff and then use a for-generate
statement loop that instantiates and connects them together.

Could anybody tell me, why:


signal clk : std_logic_vector(0 to 3);

gen_gueues : for i in 0 to NUM generate
process (clk)
begin
if clk(i)'event and clk(i)='0' then
queue(i) <= ldata(i);
end if;
end process;
end generate;

is not allowed? This works in Cadence Leapfrog for simulation, but
Synopys Design Analyzer gives an error during synthesis.
Click to expand...
I guess that Synopsys's Design Compiler don't like the idea of
generating processes. DC is well known to be quite limited in it's
support of VHDL constructs, e.g. only generics of integer type is
allowed, even though naturals should make no difference.

They're coming out with a new frontend based on Presto, but it's still
beta. We got the beta to break in spectacular ways, e.g. replacing an
"i" with a "j" could get a for-loop to work. At that point, we
realized the new frontend wasn't ready for prime time (no [tool] pun
intended).


/Kai
 
Hi Ralf,

Have you see that you demand to connect a bus (clk), and use only 1 bit
(depending of i).

What is the value of NUM ? greater than 3 ?

And finally, what is the error message ?

JaI

Ralf Hildebrandt wrote:

JJ wrote:

You need to create a component model for the ff and then use a
for-generate
statement loop that instantiates and connects them together.


Could anybody tell me, why:


signal clk : std_logic_vector(0 to 3);

gen_gueues : for i in 0 to NUM generate
process (clk)
begin
if clk(i)'event and clk(i)='0' then
queue(i) <= ldata(i);
end if;
end process;
end generate;


is not allowed? This works in Cadence Leapfrog for simulation, but
Synopys Design Analyzer gives an error during synthesis.


Ralf
Click to expand...
 
Hi MM,

See lrm, section 9.3 Generate Statement.

for..generate is a generate statement, and generate statements are
concurential statement.

process is a sequential statement, and sequential statement doesn't
embedded concurential statement.

JaI

MM wrote:

Hi all,

Is the code below valid (including for synthesis)?


signal clk : std_logic_vector(0 to 3);

PROC:
process (clk)
begin
LP1:
for i in 0 to NUM loop
if clk(i)'event and clk(i)='0' then
queue(i) <= ldata(i);
end if;
end loop;
end process;

Thanks,
/Mikhail
Click to expand...
 
Just an Illusion <illusion_to_net@yahoo.fr> wrote in message news:<40D6DF2D.1020100@yahoo.fr>...
Hi MM,

See lrm, section 9.3 Generate Statement.

for..generate is a generate statement, and generate statements are
concurential statement.

process is a sequential statement, and sequential statement doesn't
embedded concurential statement.

JaI
Click to expand...
Hi,

A process is a concurrent statement, the statements within a process are sequential.

Steven
 
Hi Steve,

You are rigth, I a met a short cut in my explanation.

Thx,
JaI

steven wrote:

Just an Illusion <illusion_to_net@yahoo.fr> wrote in message news:<40D6DF2D.1020100@yahoo.fr>...


Hi MM,

See lrm, section 9.3 Generate Statement.

for..generate is a generate statement, and generate statements are
concurential statement.

process is a sequential statement, and sequential statement doesn't
embedded concurential statement.

JaI




Hi,

A process is a concurrent statement, the statements within a process are sequential.

Steven
Click to expand...
 
Ralf Hildebrandt <Ralf-Hildebrandt@gmx.de> wrote in message news:<2jicl6F11lpg8U3@uni-berlin.de>...
JJ wrote:

You need to create a component model for the ff and then use a for-generate
statement loop that instantiates and connects them together.

Could anybody tell me, why:


signal clk : std_logic_vector(0 to 3);

gen_gueues : for i in 0 to NUM generate
process (clk)
begin
if clk(i)'event and clk(i)='0' then
queue(i) <= ldata(i);
end if;
end process;
end generate;


is not allowed? This works in Cadence Leapfrog for simulation, but
Synopys Design Analyzer gives an error during synthesis.


Ralf
Click to expand...

Hi,

It's not very clear what you are trying a acheive - you should try to
include a full example. For example, is it NUM queues, or a single
queue of depth NUM, or is queue just a single register of width NUM ?

Using an array of clocks is not something that I would expect to see.

The following code generates a single bit delay line of depth g_Delay
using a generate statement. Note that special handling of the first
register, where the input to the Delay line is registered.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.NUMERIC_STD.all;

ENTITY DelayReg IS
GENERIC(
g_Delay : natural := 1
);
PORT(
D : IN std_ulogic;
clock : IN std_ulogic;
nreset : IN std_ulogic;
Q : OUT std_ulogic
);

-- Declarations

END DelayReg ;

--
ARCHITECTURE rtl OF DelayReg IS

-- Delay Register

signal Delay_r : std_ulogic_vector(g_Delay-1 downto 0) ;

BEGIN


g0 : for DelayReg in 0 to g_Delay-1 generate
g1 : if DelayReg=0 generate
process(clock,nreset)
begin
if (nreset='0') then
Delay_r(DelayReg) <= '0' ;
elsif (clock'event and clock='1') then
Delay_r(DelayReg) <= D ;
end if ; -- clock/reset
end process ; -- Delay_p
end generate ;
g2 : if DelayReg>0 generate
process(clock,nreset)
begin
if (nreset='0') then
Delay_r(DelayReg) <= '0' ;
elsif (clock'event and clock='1') then
Delay_r(DelayReg) <= Delay_r(DelayReg-1) ;
end if ; -- clock/reset
end process ; -- Delay_p
end generate ;
end generate ;


-- Output Drive

Q <= Delay_r(g_Delay-1) ;

END rtl;

An alternative without the generate:

ARCHITECTURE rtl1 OF DelayReg IS

-- Delay Register

signal Delay_r : std_ulogic_vector(g_Delay-1 downto 0) ;

BEGIN


process(clock,nreset)
begin
if (nreset='0') then
Delay_r <= (others => '0') ;
elsif (clock'event and clock='1') then
Delay_r(0) <= D ;
for i in 1 to Delay_r'length loop
Delay_r(i) <= Delay_r(i-1) ;
end loop ;
end if ; -- clock/reset
end process ; -- Delay_p
end generate ;


-- Output Drive

Q <= Delay_r(g_Delay-1) ;

END rtl1;

It should be possible to modify these examples to your requirements,

Steven
 
Just an Illusion wrote:


Have you see that you demand to connect a bus (clk), and use only 1 bit
(depending of i).

What is the value of NUM ? greater than 3 ?

And finally, what is the error message ?
Click to expand...
O.k. - here is an example - a asyncronous counter, that I have used in
one of my designs:

For my architecture the following generic parameter is given in the entity:

generic(
timerwidth : integer:=5 );


A vector is defined with:
signal cnt_async : std_ulogic_vector(timerwidth-2 downto 0);


Now I wanted to model an asynchronous counter:

gen_cnt_async : for N in 1 to timerwidth-2 generate
process(por_n,clk_rc_len,reset_cnt_async,cnt_async)
begin
if (por_n='0' OR clk_rc_len='0' OR reset_cnt_async='1') then
cnt_async(N)<='0';
elsif falling_edge(cnt_async(N-1)) then
cnt_async(N)<=NOT(cnt_async(N));
end if;
end process;
end generate;


I used Synopsys DesignAnalyzer 2003.06. During

analyze -format vhdl {"<my_behavior.vhd>"}

I got this error message

Error: Arbitraty expression for bussed clock index is not supported.
(VHDL-284)


Behavioral simulation in Cadence Leapfrog was running fine without error.
If I unroll the generic expression, everything is fine even in Synopsys
Design Analyzer. The following synthesizes and simulates (with SDF
backannotation) well:

process(por_n,clk_rc_len,reset_cnt_async,cnt_async)
begin
if (por_n='0' OR clk_rc_len='0' OR reset_cnt_async='1') then
cnt_async(1)<='0';
elsif falling_edge(cnt_async(0)) then
cnt_async(1)<=NOT(cnt_async(1));
end if;
end process;

process(por_n,clk_rc_len,reset_cnt_async,cnt_async)
begin
if (por_n='0' OR clk_rc_len='0' OR reset_cnt_async='1') then
cnt_async(2)<='0';
elsif falling_edge(cnt_async(1)) then
cnt_async(2)<=NOT(cnt_async(2));
end if;
end process;

process(por_n,clk_rc_len,reset_cnt_async,cnt_async)
begin
if (por_n='0' OR clk_rc_len='0' OR reset_cnt_async='1') then
cnt_async(3)<='0';
elsif falling_edge(cnt_async(2)) then
cnt_async(3)<=NOT(cnt_async(3));
end if;
end process;


Maybe it is only a problem of my synthesis tool, that simply is "too
stupid" for it. ;-)

Ralf
 
On Tue, 22 Jun 2004 16:23:16 +0200, Ralf Hildebrandt <Ralf-Hildebrandt@gmx.de>
wrote:

gen_cnt_async : for N in 1 to timerwidth-2 generate
process(por_n,clk_rc_len,reset_cnt_async,cnt_async)
begin
if (por_n='0' OR clk_rc_len='0' OR reset_cnt_async='1') then
cnt_async(N)<='0';
elsif falling_edge(cnt_async(N-1)) then
cnt_async(N)<=NOT(cnt_async(N));
end if;
end process;
end generate;

I used Synopsys DesignAnalyzer 2003.06. During

analyze -format vhdl {"<my_behavior.vhd>"}

I got this error message

Error: Arbitraty expression for bussed clock index is not supported.
(VHDL-284)
Click to expand...
Would it be acceptable to create a 1-bit counter as a component, and generate N
instances of that component, using the generate loop to extract a single clock
signal from the vector? I hope THAT would get through the synthesis tool...

- Brian
 
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