Feedback from design module to the testbench

[kb33]

Hi,

I have a free running counter that co-ordinates the working of the
other modules in my design. This counter is run using the system
clock. During simulation, I would like the stimulus from the test
bench to be sent to the modules in the design at a certain value of
this counter. In other words, the test bench is getting a feedback
from the design counter as to when it should send the next stimulus.
Further, I want to send the stimulus at posedge of the clock. My
problem is that I do not know how to co-ordinate these two signals for
sending my signal - the positive edge of the clock and the value of
the counter at which the stimulus should be sent.

I tried with the following code in my test-bench:

reg sys_clk,
reset_n,
pkt_in_n_1,
pkt_in_n_2;

reg [31:0] pkt_bus;

wire [4:0] global_counter;

//The design under test is instantiated here; one of its output is
the global_counter

//Clock generation is done here...

initial
begin
//Initialization....

sys_clk <= 0;
reset_n <= 0;
pkt_in_n_1 <= 1;
pkt_in_n_2 <= 1;
pkt_bus <= 0;

#(2*period)
reset_n <= 1;


@(posedge sys_clk)
if (global_counter == 0)
begin
pkt_in_n_2 <= 1;
pkt_in_n_1 <= 0;
pkt_bus <= 6;
#(1*period) pkt_bus <= 0;
#(1*period) pkt_bus <= 0;
#(1*period) pkt_bus <= 5;
end


@(posedge sys_clk)
if (global_counter == 16)
begin
pkt_in_n_2 <= 1;
pkt_in_n_1 <= 0;
pkt_bus <= 5;
#(1*period) pkt_bus <= 0;
#(1*period) pkt_bus <= 0;
#(1*period) pkt_bus <= 8;
end

//......and so on.

Obviously, the above stimulus is not working. Can somebody tell me a
way to do this?

Thanks
Kanchan

 

[Alex]

On Feb 12, 1:24 pm, "kb33" <kanchan.devarako...@gmail.com> wrote:

Hi,

I have a free running counter that co-ordinates the working of the
other modules in my design. This counter is run using the system
clock. During simulation, I would like the stimulus from the test
bench to be sent to the modules in the design at a certain value of
this counter. In other words, the test bench is getting a feedback
from the design counter as to when it should send the next stimulus.
Further, I want to send the stimulus at posedge of the clock. My
problem is that I do not know how to co-ordinate these two signals for
sending my signal - the positive edge of the clock and the value of
the counter at which the stimulus should be sent.

I tried with the following code in my test-bench:

reg sys_clk,
reset_n,
pkt_in_n_1,
pkt_in_n_2;

reg [31:0] pkt_bus;

wire [4:0] global_counter;

//The design under test is instantiated here; one of its output is
the global_counter

//Clock generation is done here...

initial
begin
//Initialization....

sys_clk <= 0;
reset_n <= 0;
pkt_in_n_1 <= 1;
pkt_in_n_2 <= 1;
pkt_bus <= 0;

#(2*period)
reset_n <= 1;

wait(global_counter == 0);

@(posedge sys_clk)
begin
pkt_in_n_2 <= 1;
pkt_in_n_1 <= 0;
pkt_bus <= 6;
#(1*period) pkt_bus <= 0;
#(1*period) pkt_bus <= 0;
#(1*period) pkt_bus <= 5;
end

wait (global_counter == 16);
@(posedge sys_clk)
begin
pkt_in_n_2 <= 1;
pkt_in_n_1 <= 0;
pkt_bus <= 5;
#(1*period) pkt_bus <= 0;
#(1*period) pkt_bus <= 0;
#(1*period) pkt_bus <= 8;
end

//......and so on.

Obviously, the above stimulus is not working. Can somebody tell me a
way to do this?

Thanks
Kanchan

Pls see my code changes above.
-Alex