FC II & Generic

[Marek Ponca]

hi,

is there some known bug around using generics in FPGA Compiler II ?

I tried this simple code (package, component and its instance see
bellow),
FPGA Compiler II v3.7 gives this error message:

HDL-353:
Error: Can't find type information (.typ file) for type
ANALOGMASTER.PKG_ANAOGMASTER.WORD_A_I

What does this mean ?


thanks,
Marek


Proposed code:
---------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

PACKAGE pkg_pokus IS

-- ADDRESS WORD length
constant ADDR_WORD_LENGTH : natural range 1 to 16 := 10;

-- type of the ADDRESS WORD
subtype ADDR_WORD is std_logic_vector(ADDR_WORD_LENGTH-1 downto 0);

-- type of the ADDR_integer
subtype WORD_A_i is natural range 0 to 2**ADDR_WORD_LENGTH;

-- Some constant
constant PROG_REG_ADDR : WORD_A_i :=
to_integer(to_unsigned(16#3ff#,ADDR_WORD_LENGTH));

END pkg_pokus;


------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

LIBRARY AnalogMaster;
USE AnalogMaster.Pkg_pokus.all;

ENTITY ADDR_DEC IS
GENERIC(
reg_addr : WORD_A_i := 0
);
PORT(
addr : IN ADDR_WORD;
cs_n : OUT std_logic
);

END ADDR_DEC ;

ARCHITECTURE addr_dec OF ADDR_DEC IS
BEGIN

process(ADDR)
begin
if ADDR = std_logic_vector(to_unsigned(REG_ADDR,ADDR_WORD_LENGTH)) then
CS_N <= '0';
else
CS_N <= '1';
end if;
end process;
END addr_dec;

-------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

LIBRARY AnalogMaster;
USE AnalogMaster.Pkg_pokus.all;

ENTITY pokus IS
PORT(
addr : IN ADDR_WORD;
cs_n : OUT std_logic
);
END pokus ;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

LIBRARY AnalogMaster;
USE AnalogMaster.Pkg_pokus.all;

ARCHITECTURE struct OF pokus IS

COMPONENT ADDR_DEC
GENERIC (reg_addr : WORD_A_i := 0);
PORT (
addr : IN ADDR_WORD ;
cs_n : OUT std_logic
);
END COMPONENT;

BEGIN
-- Instance port mappings.
I0 : ADDR_DEC
GENERIC MAP (
reg_addr => 22
)
PORT MAP (
addr => addr,
cs_n => cs_n
);
END struct;

 

[Marcin]

Hello Marek,

For generics with custom types you have to create additional .typ
file. If you are using gui double-click on the error message to see
the help, it will also advise you how to create this file. I must say
that I have never played with that - this is only what I noticed.

HTH,
Marcin

Marek Ponca <marek.ponca@tu-ilmenau.de> wrote in message news:<3FBE3043.5971171A@tu-ilmenau.de>...

hi,

is there some known bug around using generics in FPGA Compiler II ?

I tried this simple code (package, component and its instance see
bellow),
FPGA Compiler II v3.7 gives this error message:
HDL-353:
Error: Can't find type information (.typ file) for type
ANALOGMASTER.PKG_ANAOGMASTER.WORD_A_I

What does this mean ?


thanks,
Marek


Proposed code:
---------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

PACKAGE pkg_pokus IS

-- ADDRESS WORD length
constant ADDR_WORD_LENGTH : natural range 1 to 16 := 10;

-- type of the ADDRESS WORD
subtype ADDR_WORD is std_logic_vector(ADDR_WORD_LENGTH-1 downto 0);

-- type of the ADDR_integer
subtype WORD_A_i is natural range 0 to 2**ADDR_WORD_LENGTH;

-- Some constant
constant PROG_REG_ADDR : WORD_A_i :=
to_integer(to_unsigned(16#3ff#,ADDR_WORD_LENGTH));

END pkg_pokus;


------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

LIBRARY AnalogMaster;
USE AnalogMaster.Pkg_pokus.all;

ENTITY ADDR_DEC IS
GENERIC(
reg_addr : WORD_A_i := 0
);
PORT(
addr : IN ADDR_WORD;
cs_n : OUT std_logic
);

END ADDR_DEC ;

ARCHITECTURE addr_dec OF ADDR_DEC IS
BEGIN

process(ADDR)
begin
if ADDR = std_logic_vector(to_unsigned(REG_ADDR,ADDR_WORD_LENGTH)) then
CS_N <= '0';
else
CS_N <= '1';
end if;
end process;
END addr_dec;

-------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

LIBRARY AnalogMaster;
USE AnalogMaster.Pkg_pokus.all;

ENTITY pokus IS
PORT(
addr : IN ADDR_WORD;
cs_n : OUT std_logic
);
END pokus ;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

LIBRARY AnalogMaster;
USE AnalogMaster.Pkg_pokus.all;

ARCHITECTURE struct OF pokus IS

COMPONENT ADDR_DEC
GENERIC (reg_addr : WORD_A_i := 0);
PORT (
addr : IN ADDR_WORD ;
cs_n : OUT std_logic
);
END COMPONENT;

BEGIN
-- Instance port mappings.
I0 : ADDR_DEC
GENERIC MAP (
reg_addr => 22
)
PORT MAP (
addr => addr,
cs_n => cs_n
);
END struct;