favorite circuit for 8 - 20us pulses

[Winfield Hill]

Standard pulses: tr 8us, td 20us to 50% down.
What's your favorite circuit for making device
test pulses, from a square wave I suppose.


--
Thanks,
- Win

 

[piglet]

On 20/06/2019 10:37 am, Winfield Hill wrote:

Standard pulses: tr 8us, td 20us to 50% down.
What's your favorite circuit for making device
test pulses, from a square wave I suppose.

Is this logic level or HV? If logic then I am unclear on the
terminology, do you mean 8us rise time, 20us delay? Do you want output
crisp logic edges or slow exponential rise/fall? My starting point would
be RC either w-w/o schmitt HC14

If HV then cap discharge I guess?

piglet

 

[Bill Sloman]

On Thursday, June 20, 2019 at 11:38:12 AM UTC+2, Winfield Hill wrote:

Standard pulses: tr 8us, td 20us to 50% down.
What's your favorite circuit for making device
test pulses, from a square wave I suppose.

74121 or 74221 (dual) monostable.

About 0.1% stable with a good quality capacitor, and a 19mm potentiometer trimmer lets you set up exactly the pulse width (or delay) you want.

If you want to count edges from a square wave

https://assets.nexperia.com/documents/data-sheet/74HC40103.pdf

is nice. You can clock it at up to 10 MHz (if you run it off a 5v rail).

This is obvious stuff. What kind of part do you actually want?

--
Bill Sloman, Sydney

 

[George Herold]

On Thursday, June 20, 2019 at 6:49:45 AM UTC-4, piglet wrote:

On 20/06/2019 10:37 am, Winfield Hill wrote:
Standard pulses: tr 8us, td 20us to 50% down.
What's your favorite circuit for making device
test pulses, from a square wave I suppose.



Is this logic level or HV? If logic then I am unclear on the
terminology, do you mean 8us rise time, 20us delay? Do you want output
crisp logic edges or slow exponential rise/fall? My starting point would
be RC either w-w/o schmitt HC14

If HV then cap discharge I guess?

piglet

It sounds like Win wants 8 and 20 us rise and fall times.. but I'm not sure.

George H.

 

On 20 Jun 2019 07:25:27 -0700, Winfield Hill <winfieldhill@yahoo.com>
wrote:

piglet wrote...

On 20/06/2019 10:37 am, Winfield Hill wrote:
Standard pulses: tr 8us, td 20us to 50% down.
What's your favorite circuit for making device
test pulses, from a square wave I suppose.

Is this logic level or HV? If logic then I am
unclear on the terminology, do you mean 8us rise
time, 20us delay?

This is standard terminology. First, these
are current pulses, with high compliance-voltage
capability, higher than the breakdown voltages
of the D.U.T. The 8us tr refers to the time
to reach the peak current, and 20us td refers
to the delay time, from the beginning, for the
pulse to drop to 50% of the peak value. You
will recognize this pulse's waveform drawing.

What is the required peak current ? 100 kA ? Positive or negative peak
?6

 

[Winfield Hill]

piglet wrote...

On 20/06/2019 10:37 am, Winfield Hill wrote:
Standard pulses: tr 8us, td 20us to 50% down.
What's your favorite circuit for making device
test pulses, from a square wave I suppose.

Is this logic level or HV? If logic then I am
unclear on the terminology, do you mean 8us rise
time, 20us delay?

This is standard terminology. First, these
are current pulses, with high compliance-voltage
capability, higher than the breakdown voltages
of the D.U.T. The 8us tr refers to the time
to reach the peak current, and 20us td refers
to the delay time, from the beginning, for the
pulse to drop to 50% of the peak value. You
will recognize this pulse's waveform drawing.


--
Thanks,
- Win

 

[Tim Williams]

Y'mean an IEC 61000-4-5 surge?

You need a network like this:
https://www.seventransistorlabs.com/Images/8-20_Surge_Network.png

Note that the impedance is not resistive, it's impedance abuse because the
waveform depends on load impedance as well. Namely it's a 1.5-50 open
circuit and 8-20 short circuit, and the ratio of peaks is the "impedance",
which is supposed to be 2 ohms.

There's something like 10 or 20% loss in this network IIRC, so set C1
IC={desired peak voltage * 1.1} or so.

I've also made an automotive load dump model which is square-wave-based, for
SPICE purposes only (I wouldn't recommend building it that way ).

Tim

--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Design
Website: https://www.seventransistorlabs.com/

"Winfield Hill" <winfieldhill@yahoo.com> wrote in message
news:qefk5j01ned@drn.newsguy.com...

Standard pulses: tr 8us, td 20us to 50% down.
What's your favorite circuit for making device
test pulses, from a square wave I suppose.


--
Thanks,
- Win

 

[Winfield Hill]

upsidedown@downunder.com wrote...

Winfield Hill wrote:
piglet wrote...
On 20/06/2019 10:37 am, Winfield Hill wrote:
Standard pulses: tr 8us, td 20us to 50% down.
What's your favorite circuit for making device
test pulses, from a square wave I suppose.

Is this logic level or HV? If logic then I am
unclear on the terminology, do you mean 8us rise
time, 20us delay?

This is standard terminology. First, these
are current pulses, with high compliance-voltage
capability, higher than the breakdown voltages
of the D.U.T. The 8us tr refers to the time
to reach the peak current, and 20us td refers
to the delay time, from the beginning, for the
pulse to drop to 50% of the peak value. You
will recognize this pulse's waveform drawing.

What is the required peak current ? 100 kA ?
Positive or negative peak?

10A is a common value. Need both polarities.


--
Thanks,
- Win

 

[bitrex]

On 6/20/19 5:37 AM, Winfield Hill wrote:

Standard pulses: tr 8us, td 20us to 50% down.
What's your favorite circuit for making device
test pulses, from a square wave I suppose.

Only incidentally related but a 2D21 thyratron sawtooth oscillator has
ripping fast edges at the end of the ramp (de-ionization time?)

suitably divided down and buffered a 10 MHz GBW 20v/uSec op amp can
barely keep up with it.

 

[Jon Elson]

On Thu, 20 Jun 2019 07:25:27 -0700, Winfield Hill wrote:

piglet wrote...

On 20/06/2019 10:37 am, Winfield Hill wrote:
Standard pulses: tr 8us, td 20us to 50% down. What's your favorite
circuit for making device test pulses, from a square wave I suppose.

Is this logic level or HV? If logic then I am unclear on the
terminology, do you mean 8us rise time, 20us delay?

This is standard terminology. First, these are current pulses, with
high compliance-voltage capability, higher than the breakdown voltages
of the D.U.T. The 8us tr refers to the time to reach the peak
current, and 20us td refers to the delay time, from the beginning, for
the pulse to drop to 50% of the peak value. You will recognize this
pulse's waveform drawing.

Oh, the 8/20 sounds like ESD testing. I'm pretty sure the ESD testing
"guns" use a spark gap to trigger the pulse, and a network of R's and C's
to shape it and control current. This must all be public domain stuff by
now. So, all you need for these is a HV power supply to charge the first
cap.

Jon

 

On 20 Jun 2019 08:28:07 -0700, Winfield Hill <winfieldhill@yahoo.com>
wrote:

upsidedown@downunder.com wrote...

Winfield Hill wrote:
piglet wrote...
On 20/06/2019 10:37 am, Winfield Hill wrote:
Standard pulses: tr 8us, td 20us to 50% down.
What's your favorite circuit for making device
test pulses, from a square wave I suppose.

Is this logic level or HV? If logic then I am
unclear on the terminology, do you mean 8us rise
time, 20us delay?

This is standard terminology. First, these
are current pulses, with high compliance-voltage
capability, higher than the breakdown voltages
of the D.U.T. The 8us tr refers to the time
to reach the peak current, and 20us td refers
to the delay time, from the beginning, for the
pulse to drop to 50% of the peak value. You
will recognize this pulse's waveform drawing.

What is the required peak current ? 100 kA ?
Positive or negative peak?

10A is a common value. Need both polarities.

That is pretty low, it doesn't even fulfill IEC 61000-4-5 Class 0 (25
V / 12.5 A into 2 ohm), intended for well protected environment.

More approximate for long signal cables would be Class 3 (2 kV / 1kA
into 2 ohm or 2 kV / 48 A into 42 ohm) or for mains connected devices
Class 4 (4 kV / 2kA into 2 ohm).

 

[whit3rd]

On Thursday, June 20, 2019 at 2:38:12 AM UTC-7, Winfield Hill wrote:

Standard pulses: tr 8us, td 20us to 50% down.
What's your favorite circuit for making device
test pulses, from a square wave I suppose.

A Moog synthesizer's solution to the pulse problem is (basically) a three-transistor
multiplier. You capacitor-load it and the rise and fall times depend on the current
programmed into the emitter. Set the multiplier input positive for rise, negative for fall,
and program the current differently in the two phases...

Another is the gas-filled tube; conductance rises quickly when it avalanches, drops
slowly as the gas cools. It'd be a hard problem to match risetime/falltime to
a model, though, because there's pressure/geometry/quench-gas variables to
consider. Still, if you need to make a CERN deector that's the size of a
three-story building, fill gas is the economic solution at that scale. Georges
Charpak earned his Nobel prize doing that.

 

[piglet]

On 20/06/2019 3:25 pm, Winfield Hill wrote:

piglet wrote...

On 20/06/2019 10:37 am, Winfield Hill wrote:
Standard pulses: tr 8us, td 20us to 50% down.
What's your favorite circuit for making device
test pulses, from a square wave I suppose.

Is this logic level or HV? If logic then I am
unclear on the terminology, do you mean 8us rise
time, 20us delay?

This is standard terminology. First, these
are current pulses, with high compliance-voltage
capability, higher than the breakdown voltages
of the D.U.T. The 8us tr refers to the time
to reach the peak current, and 20us td refers
to the delay time, from the beginning, for the
pulse to drop to 50% of the peak value. You
will recognize this pulse's waveform drawing.

Thanks, I realised that some after posting when I connected it to your
other posts on using a BJT e-b for ESD protection!

I think that while the 8/20us wave may have a use representing line
borne transients it is way too slow for simulating ESD events which can
have very steep rising edge.

piglet

 

[Winfield Hill]

piglet wrote...

I think that while the 8/20us wave may have a use
representing line-borne transients it is way too
slow for simulating ESD events which can have
very steep rising edge.

Yes, but if our part can pass 8/20, it can also
pass faster risetimes, provided there's a little
capacitance at hand. On my sensor stick, each
I2C line got a 100pF cap, along with the CD143A.
Blast away! (BTW, for anybody who remembers that
discussion, my final choice for a data cable was
a miniDIN with gold pins, CS-DNPDM6MMX2-006 from
Cable-On-Demand, $5 each. Surprise! It came
with a braid shield, so we're double safe.)


--
Thanks,
- Win