Fatal: (vsim-3613) Top-level instantiation of Verilog optimi

[gck]

I compile following program and its getting compiled without any error
`timescale 1ns/1ns

module delaybuf(output y,
input a);
buf u1 (y,a);

specify
(a*>y)=5;
endspecify

endmodule // delaybuf

but when I am trying to simulate it, error shows
Fatal: (vsim-3613) Top-level instantiation of Verilog optimized cell
'delaybuf' is not allowed.
don't get simulate.
I using Questasim 6.2b
Thanks in advance

 

[Jonathan Bromley]

On Sat, 29 Nov 2008 03:34:36 -0800 (PST), gck <gkhedkar@gmail.com>
wrote:

I compile following program and its getting compiled without any error
`timescale 1ns/1ns

module delaybuf(output y,
input a);
buf u1 (y,a);

specify
(a*>y)=5;
endspecify

endmodule // delaybuf

It's not a program, it's a module definition.

but when I am trying to simulate it, error shows
Fatal: (vsim-3613) Top-level instantiation of Verilog optimized cell
'delaybuf' is not allowed.
don't get simulate.

You are trying to simulate a buffer device that is
lying upside-down on the bench with its legs in the air.
This is unlikely to be useful. Consider writing
a testbench to provide some stimulus for your buffer.

--
Jonathan Bromley, Consultant

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