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Martin Euredjian

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Does Altera have devices with I/O that can drive (or be driven) at 300 to
400MHz? Internal logic would have to run at 1/2 that frequency. RLDRAM II
is the application.

Thanks,


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Martin Euredjian

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Hi Martin,

Does Altera have devices with I/O that can drive (or be driven) at 300 to
400MHz? Internal logic would have to run at 1/2 that frequency. RLDRAM II
is the application.
Click to expand...
From our documentation, I see that Stratix devices can support up to 200 Mhz
RLDRAM II using 1.8V HSTL signaling. RLDRAM runs at DDR, so that equates to
400 Mb/s per pin. I'm not sure if that answers your question -- I'd suggest
contacting Altera (Altera Applications/Sales, that is...) to find out more.

Regards,

Paul Leventis
Altera
 
RLDRAM II can (will) hit 400MHz (2.5ns cycle) actual clock rate. Of course,
still DDR, so 800Mb/s/pin peak.


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Martin Euredjian

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"Paul Leventis (at home)" <paul.leventis@utoronto.ca> wrote in message
news:4EmNb.28970$ZuL1.1332@twister01.bloor.is.net.cable.rogers.com...
Hi Martin,

Does Altera have devices with I/O that can drive (or be driven) at 300
to
400MHz? Internal logic would have to run at 1/2 that frequency. RLDRAM
II
is the application.

From our documentation, I see that Stratix devices can support up to 200
Mhz
RLDRAM II using 1.8V HSTL signaling. RLDRAM runs at DDR, so that equates
to
400 Mb/s per pin. I'm not sure if that answers your question -- I'd
suggest
contacting Altera (Altera Applications/Sales, that is...) to find out
more.

Regards,

Paul Leventis
Altera
Click to expand...
 
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:r2nNb.1094$746.125@newssvr29.news.prodigy.com...
RLDRAM II can (will) hit 400MHz (2.5ns cycle) actual clock rate. Of
course,
still DDR, so 800Mb/s/pin peak.
Click to expand...
Martin -

Virtex-II (and Pro) should be able to handle that. Xilinx's SPI-4.2 and
HyperTransport cores run up to 400MHz DDR (800Mbps per pin). I assume
RLDRAM has separate (uni-directional) read and write paths? I can't
imagine anything running bi-directional at those rates.

Robert
 
It's a single data path.

It looks like none of the current FPGA's will support this in non-trivial
application.


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
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"Robert Sefton" <rsefton@abc.net> wrote in message
news:bu53b6$dpfal$1@ID-212988.news.uni-berlin.de...
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:r2nNb.1094$746.125@newssvr29.news.prodigy.com...
RLDRAM II can (will) hit 400MHz (2.5ns cycle) actual clock rate. Of
course,
still DDR, so 800Mb/s/pin peak.


Martin -

Virtex-II (and Pro) should be able to handle that. Xilinx's SPI-4.2 and
HyperTransport cores run up to 400MHz DDR (800Mbps per pin). I assume
RLDRAM has separate (uni-directional) read and write paths? I can't
imagine anything running bi-directional at those rates.

Robert
Click to expand...
 
On the Stratix FPGA, -5 (fastest) speed grade, flip-chip package, the
clock input can handle up to 400 MHz for 1.5 or 1.8 V HSTL. The
fastest output clock is 225-250 MHz depending on whether this is HSTL
Class I or II. So this alone precludes a 400 MHz RLDRAM II interface.
Furthermore, there's more to the interface than toggle rate - for
example, skew between the pins will impact timing.

There is another comment in this thread about SPI-4.2 and
HyperTransport running at 400 MHz DDR (800 Mbps per pin) on FPGAs.
This is true, but keep in mind that that these are low-swing
differential IO standards which can generally toggle faster than
single-ended standards like HSTL. This is how FPGAs have had 840 Mbps
LVDS since APEX 20KE was released some time ago. Also, some FPGAs
(like Stratix) have a built in serial/parallel converter (and vice
versa) so that the programmable logic never sees the high speed
signal. For example, with an 800 Mbps SPI-4.2, you may have an 4:1
converter so that the logic in the device runs at 200 MHz. There's no
such converter for HSTL other than the double-data rate IO buffers.

Regards,
Greg Steinke
gregs@altera.com


"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<dRDNb.11195$gD6.6510@newssvr25.news.prodigy.com>...
It's a single data path.

It looks like none of the current FPGA's will support this in non-trivial
application.


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"



"Robert Sefton" <rsefton@abc.net> wrote in message
news:bu53b6$dpfal$1@ID-212988.news.uni-berlin.de...
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:r2nNb.1094$746.125@newssvr29.news.prodigy.com...
RLDRAM II can (will) hit 400MHz (2.5ns cycle) actual clock rate. Of
course,
still DDR, so 800Mb/s/pin peak.


Martin -

Virtex-II (and Pro) should be able to handle that. Xilinx's SPI-4.2 and
HyperTransport cores run up to 400MHz DDR (800Mbps per pin). I assume
RLDRAM has separate (uni-directional) read and write paths? I can't
imagine anything running bi-directional at those rates.

Robert
Click to expand...
 
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<dRDNb.11195$gD6.6510@newssvr25.news.prodigy.com>...
It's a single data path.

It looks like none of the current FPGA's will support this in non-trivial
application.


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian
Click to expand...
Indeed, the X Avnet? board I previously mentioned was RLDRAM1 about
300MHz DDR and RAS cycle 25ns IIRC. I don't see why you couldn't use
RLDRAM2 at the lower DDR rates but still get 20ns RAS cycle at least
its as close to 10ns SRAM as you will get for now. I also mistakenly
said the IOs were split, I was looking at another Cypress SRAM at same
time.

If anyone does get/see RLDRAM2 running on X esp Spartan3, I'd like to
know about it too, but I can live with lower IO rates, shame about the
common IOs.

johnjakson_usa_com
 
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