fast compare unit

[Divyang M]

Hi,

I am finding the max of 18 std_logic_vector signals in vhdl. I have
the operation broken down into stages so that it takes 5 clock cycles
to get 1 compare unit, but I would like to get this done in 3 clock
cycles since I have a new set of 18 signals coming in every 4 cycles.
Is this possible to do this in 3 cycles and also get a frequency of 70
MHz for this unit? I am using Altera Stratix S80 chips. I was thinking
of comparing 3 values at a time, but I am not sure if that will
synthesize..if anyone has done this..I would greatly appreciate your
insight and help.

For eg., currently I am doing as such (i'm giving an example for 6
signals)
-- stage 1
if (s1 >= s2) then
s1_1 <= s1;
else
s1_1 <= s2;
end if;

if (s3 >= s4) then
s2_1 <= s3;
else
s2_1 <= s4;
end if;

if (s5 >= s6) then
s3_1 <= s5;
else
s3_1 <= s6;
end if;

-- stage 2
if (s1_1 >= s2_1)
s1_2 <= s1_1;
else
s1_2 <= s2_1;
end if;

s2_2 <= s3_1;

-- stage 3
if (s1_2 >= s2_2)
result <= s1_2;
else
result <= s2_2;
end if;

Thanks,

Divyang M

 

[jens]

A pipelined design should do the trick.