Fanout using free vias in Orcad9.2

[hakim]

Hello,
I have a 0.8mm pitch BGA device to be routed. It has 256 balls
arranged as three rows on the periphery and all ground and a few
signal pins inside. I have ample space on the board to fanout. I have
arranged an array of free via matrix around the device and assigned
them to appropriate nets.
To fanout the inner row i have placed free vias under pad as i had
no other placement option keeping in mind the constraints of by board
maker). Now can someone please tell me how do i fanout using these
free vias. Using the fanout command, tries to place additional vias
and consequently gives up. In short how do i get zero length fanouts?

Regards
Hakim

 

[qrk]

On 23 Nov 2003 03:07:11 -0800, hakimraja@hotmail.com (hakim) wrote:

Hello,
I have a 0.8mm pitch BGA device to be routed. It has 256 balls
arranged as three rows on the periphery and all ground and a few
signal pins inside. I have ample space on the board to fanout. I have
arranged an array of free via matrix around the device and assigned
them to appropriate nets.
To fanout the inner row i have placed free vias under pad as i had
no other placement option keeping in mind the constraints of by board
maker). Now can someone please tell me how do i fanout using these
free vias. Using the fanout command, tries to place additional vias
and consequently gives up. In short how do i get zero length fanouts?

Regards
Hakim

Why don't you modify the part and use thru holes on the pads where you
need zero length traces. This is probably easier than dealing with
zero length fanouts which probably don't exist.

Mark

 

[hakim]

qrk <mark@reson.DELETE.ME.com> wrote in message news:<8pd5svkqkt0nejhfv5klj8i3thklmnkc4p@4ax.com>...

On 23 Nov 2003 03:07:11 -0800, hakimraja@hotmail.com (hakim) wrote:

Hello,
I have a 0.8mm pitch BGA device to be routed. It has 256 balls
arranged as three rows on the periphery and all ground and a few
signal pins inside. I have ample space on the board to fanout. I have
arranged an array of free via matrix around the device and assigned
them to appropriate nets.
To fanout the inner row i have placed free vias under pad as i had
no other placement option keeping in mind the constraints of by board
maker). Now can someone please tell me how do i fanout using these
free vias. Using the fanout command, tries to place additional vias
and consequently gives up. In short how do i get zero length fanouts?

Regards
Hakim

Why don't you modify the part and use thru holes on the pads where you
need zero length traces. This is probably easier than dealing with
zero length fanouts which probably don't exist.

Mark

...hey that was a neat idea Mark!! i'll do that. btw another thing
i wanted to ask was this. I have added free vias all around the place
and attached them to nets VCC and GND. these nets are attached to
planes VCC and GND. I see thermal only around the vias attached to GND
but not around the VCC vias. Any clues?

Regards
Hakim

 

[hakim]

qrk <mark@reson.DELETE.ME.com> wrote in message news:<8pd5svkqkt0nejhfv5klj8i3thklmnkc4p@4ax.com>...

On 23 Nov 2003 03:07:11 -0800, hakimraja@hotmail.com (hakim) wrote:

Hello,
I have a 0.8mm pitch BGA device to be routed. It has 256 balls
arranged as three rows on the periphery and all ground and a few
signal pins inside. I have ample space on the board to fanout. I have
arranged an array of free via matrix around the device and assigned
them to appropriate nets.
To fanout the inner row i have placed free vias under pad as i had
no other placement option keeping in mind the constraints of by board
maker). Now can someone please tell me how do i fanout using these
free vias. Using the fanout command, tries to place additional vias
and consequently gives up. In short how do i get zero length fanouts?

Regards
Hakim

Why don't you modify the part and use thru holes on the pads where you
need zero length traces. This is probably easier than dealing with
zero length fanouts which probably don't exist.

Mark

Hi Mark,
i just realised one thing! while the method u suggested will
work for my GND and VCC vias, i'll have problem with my other signal
vias. I have to fan the adjacent inner signals on different layers to
avoid spacing/size violations defined by by board maker. I need to
keep a minimum annular ring of 16mil to take a connection and minimum
drill is 16mil and min spacing of 5 mil. I have two inner signal
routing layers and am using them alternately with adjacent signals.
Now if i define the padstacks as throuholes i'll have same dia pads on
all inner layers as the padstack spreadsheet has only one entry for
inner layers and so i would definitely need freevias for the
signals!!! ne more bright ideas?

Regards
Hakim