Extraction of parasitic from trace...

[Klaus Kragelund]

Hi

I am working on a high frequency design in which we in principle is using a very high frequency switch mode converter

I need low loss, so need to minimize capacitive parasitics, and also minimize inductances. They conflict of course, smaller trace has lower capacitance but higher inductance.

We use Altium for layout and have used ADS for parasitic extraction. But we cannot afford the license.

Is there a low cost alternative that is ok in terms of amount of time to get it done?

I was thinking maybe somebody has made a tool, maybe even excel, that could import the trace and image plane /traces to do a finite element analysis /model.

Any hints?

--
Klaus

 

[John Larkin]

On Sat, 07 Jan 2023 02:29:48 +0100, Klaus Kragelund
<klauskvik@hotmail.com> wrote:

Hi

I am working on a high frequency design in which we in principle is using a very high frequency switch mode converter

I need low loss, so need to minimize capacitive parasitics, and also minimize inductances. They conflict of course, smaller trace has lower capacitance but higher inductance.

We use Altium for layout and have used ADS for parasitic extraction. But we cannot afford the license.

Is there a low cost alternative that is ok in terms of amount of time to get it done?

I was thinking maybe somebody has made a tool, maybe even excel, that could import the trace and image plane /traces to do a finite element analysis /model.

Any hints?

The Saturn software does the basics for standard trace geometries.

Sonnet Lite does 2.5-D em analysis for free.

A switcher should be small enough that the speed of light is
inconsequential. How high a frequncy did you have in mind?

 

[John Larkin]

On Sat, 07 Jan 2023 02:29:48 +0100, Klaus Kragelund
<klauskvik@hotmail.com> wrote:

Hi

I am working on a high frequency design in which we in principle is using a very high frequency switch mode converter

I need low loss, so need to minimize capacitive parasitics, and also minimize inductances. They conflict of course, smaller trace has lower capacitance but higher inductance.

We use Altium for layout and have used ADS for parasitic extraction. But we cannot afford the license.

Is there a low cost alternative that is ok in terms of amount of time to get it done?

I was thinking maybe somebody has made a tool, maybe even excel, that could import the trace and image plane /traces to do a finite element analysis /model.

Any hints?

The Saturn software does the basics for standard trace geometries.

Sonnet Lite does 2.5-D em analysis for free.

A switcher should be small enough that the speed of light is
inconsequential. How high a frequncy did you have in mind?

 

[John Larkin]

On Sat, 07 Jan 2023 02:29:48 +0100, Klaus Kragelund
<klauskvik@hotmail.com> wrote:

Hi

I am working on a high frequency design in which we in principle is using a very high frequency switch mode converter

I need low loss, so need to minimize capacitive parasitics, and also minimize inductances. They conflict of course, smaller trace has lower capacitance but higher inductance.

We use Altium for layout and have used ADS for parasitic extraction. But we cannot afford the license.

Is there a low cost alternative that is ok in terms of amount of time to get it done?

I was thinking maybe somebody has made a tool, maybe even excel, that could import the trace and image plane /traces to do a finite element analysis /model.

Any hints?

The Saturn software does the basics for standard trace geometries.

Sonnet Lite does 2.5-D em analysis for free.

A switcher should be small enough that the speed of light is
inconsequential. How high a frequncy did you have in mind?

 

[John Larkin]

On Sun, 08 Jan 2023 12:39:16 +0200, upsidedown@downunder.com wrote:

On Sat, 7 Jan 2023 15:37:20 +0100, Klaus Vestergaard Kragelund
klauskvik@hotmail.com> wrote:

On 07-01-2023 13:56, John Larkin wrote:
On Sat, 07 Jan 2023 02:29:48 +0100, Klaus Kragelund
klauskvik@hotmail.com> wrote:

Hi

I am working on a high frequency design in which we in principle is using a very high frequency switch mode converter

I need low loss, so need to minimize capacitive parasitics, and also minimize inductances. They conflict of course, smaller trace has lower capacitance but higher inductance.

We use Altium for layout and have used ADS for parasitic extraction. But we cannot afford the license.

Is there a low cost alternative that is ok in terms of amount of time to get it done?

I was thinking maybe somebody has made a tool, maybe even excel, that could import the trace and image plane /traces to do a finite element analysis /model.

Any hints?

The Saturn software does the basics for standard trace geometries.

Sonnet Lite does 2.5-D em analysis for free.

Thanks, that looks quite nice.


A switcher should be small enough that the speed of light is
inconsequential. How high a frequncy did you have in mind?


It\'s not a standard switcher

Operating at 100MHz, and with 1ns switch node rise time. So even
laminate loss is important.

Sounds like VHF transmitter design

At those frequencies you also need to consider the skin dept, i.e. the
current flows only at the surface of the traces. Thus the resistive
losses of the trace is larger than on DC and you may have to use wider
traces if large currants are involved.

More important, copper that\'s shiny on the bottom. Most of the current
is on the dielectric side.

Regular PCB:

https://www.dropbox.com/s/m65gd96vs8j5qp8/PCB_foil_peel.jpg?raw=1

Isola, medium-range microwave laminate

https://www.dropbox.com/s/7nwkho3kl1zx2bl/Isola_Peel.jpg?raw=1

A serious microwave laminate is full shiny and peels with a toothpick.

 

[John Larkin]

On Sun, 08 Jan 2023 12:39:16 +0200, upsidedown@downunder.com wrote:

On Sat, 7 Jan 2023 15:37:20 +0100, Klaus Vestergaard Kragelund
klauskvik@hotmail.com> wrote:

On 07-01-2023 13:56, John Larkin wrote:
On Sat, 07 Jan 2023 02:29:48 +0100, Klaus Kragelund
klauskvik@hotmail.com> wrote:

Hi

I am working on a high frequency design in which we in principle is using a very high frequency switch mode converter

I need low loss, so need to minimize capacitive parasitics, and also minimize inductances. They conflict of course, smaller trace has lower capacitance but higher inductance.

We use Altium for layout and have used ADS for parasitic extraction. But we cannot afford the license.

Is there a low cost alternative that is ok in terms of amount of time to get it done?

I was thinking maybe somebody has made a tool, maybe even excel, that could import the trace and image plane /traces to do a finite element analysis /model.

Any hints?

The Saturn software does the basics for standard trace geometries.

Sonnet Lite does 2.5-D em analysis for free.

Thanks, that looks quite nice.


A switcher should be small enough that the speed of light is
inconsequential. How high a frequncy did you have in mind?


It\'s not a standard switcher

Operating at 100MHz, and with 1ns switch node rise time. So even
laminate loss is important.

Sounds like VHF transmitter design

At those frequencies you also need to consider the skin dept, i.e. the
current flows only at the surface of the traces. Thus the resistive
losses of the trace is larger than on DC and you may have to use wider
traces if large currants are involved.

More important, copper that\'s shiny on the bottom. Most of the current
is on the dielectric side.

Regular PCB:

https://www.dropbox.com/s/m65gd96vs8j5qp8/PCB_foil_peel.jpg?raw=1

Isola, medium-range microwave laminate

https://www.dropbox.com/s/7nwkho3kl1zx2bl/Isola_Peel.jpg?raw=1

A serious microwave laminate is full shiny and peels with a toothpick.

 

[John Larkin]

On Sun, 08 Jan 2023 12:39:16 +0200, upsidedown@downunder.com wrote:

On Sat, 7 Jan 2023 15:37:20 +0100, Klaus Vestergaard Kragelund
klauskvik@hotmail.com> wrote:

On 07-01-2023 13:56, John Larkin wrote:
On Sat, 07 Jan 2023 02:29:48 +0100, Klaus Kragelund
klauskvik@hotmail.com> wrote:

Hi

I am working on a high frequency design in which we in principle is using a very high frequency switch mode converter

I need low loss, so need to minimize capacitive parasitics, and also minimize inductances. They conflict of course, smaller trace has lower capacitance but higher inductance.

We use Altium for layout and have used ADS for parasitic extraction. But we cannot afford the license.

Is there a low cost alternative that is ok in terms of amount of time to get it done?

I was thinking maybe somebody has made a tool, maybe even excel, that could import the trace and image plane /traces to do a finite element analysis /model.

Any hints?

The Saturn software does the basics for standard trace geometries.

Sonnet Lite does 2.5-D em analysis for free.

Thanks, that looks quite nice.


A switcher should be small enough that the speed of light is
inconsequential. How high a frequncy did you have in mind?


It\'s not a standard switcher

Operating at 100MHz, and with 1ns switch node rise time. So even
laminate loss is important.

Sounds like VHF transmitter design

At those frequencies you also need to consider the skin dept, i.e. the
current flows only at the surface of the traces. Thus the resistive
losses of the trace is larger than on DC and you may have to use wider
traces if large currants are involved.

More important, copper that\'s shiny on the bottom. Most of the current
is on the dielectric side.

Regular PCB:

https://www.dropbox.com/s/m65gd96vs8j5qp8/PCB_foil_peel.jpg?raw=1

Isola, medium-range microwave laminate

https://www.dropbox.com/s/7nwkho3kl1zx2bl/Isola_Peel.jpg?raw=1

A serious microwave laminate is full shiny and peels with a toothpick.

 

[Klaus Vestergaard Kragelund]

On 07-01-2023 17:31, John Larkin wrote:

On Sat, 7 Jan 2023 15:37:20 +0100, Klaus Vestergaard Kragelund
klauskvik@hotmail.com> wrote:

On 07-01-2023 13:56, John Larkin wrote:
On Sat, 07 Jan 2023 02:29:48 +0100, Klaus Kragelund
klauskvik@hotmail.com> wrote:

Hi

I am working on a high frequency design in which we in principle is using a very high frequency switch mode converter

I need low loss, so need to minimize capacitive parasitics, and also minimize inductances. They conflict of course, smaller trace has lower capacitance but higher inductance.

We use Altium for layout and have used ADS for parasitic extraction. But we cannot afford the license.

Is there a low cost alternative that is ok in terms of amount of time to get it done?

I was thinking maybe somebody has made a tool, maybe even excel, that could import the trace and image plane /traces to do a finite element analysis /model.

Any hints?

The Saturn software does the basics for standard trace geometries.

Sonnet Lite does 2.5-D em analysis for free.

Thanks, that looks quite nice.


A switcher should be small enough that the speed of light is
inconsequential. How high a frequncy did you have in mind?


It\'s not a standard switcher

Operating at 100MHz, and with 1ns switch node rise time. So even
laminate loss is important.



Sounds like fun. GaN?

Yes, EPC GaN.

One problem we encounter is driving laser diodes fast. At 5 amps per
ns, it gets hard to wire things up. Eveny nH of inductance drops 5
volts. Tx line impedances need to be a fraction of an ohm. Most laser
diode makers don\'t seem to understand this and sure don\'t furnish IBIS
files. The laser physics can help, or hurt, and that\'s not specified.

Excactly what we are looking into also. The layout did a mistake, and we
are fixing it.

Driving Pockels Cells can have similar issues, but kilovolts.

A proper sim, device and package models, Spice, IBIS, 3D e/m sim,
thermals, PCB, is probably impossible, or would take years and
megabucks. I use instinct and Dremels.

We have used ADS so far, but no more license.

If you crowd parts to keep the electricals tight, then they get hot.
Yet another dimension in the optimization space.

The power we have is low, so we pack it very tight.

 

[Klaus Vestergaard Kragelund]

On 07-01-2023 17:31, John Larkin wrote:

On Sat, 7 Jan 2023 15:37:20 +0100, Klaus Vestergaard Kragelund
klauskvik@hotmail.com> wrote:

On 07-01-2023 13:56, John Larkin wrote:
On Sat, 07 Jan 2023 02:29:48 +0100, Klaus Kragelund
klauskvik@hotmail.com> wrote:

Hi

I am working on a high frequency design in which we in principle is using a very high frequency switch mode converter

I need low loss, so need to minimize capacitive parasitics, and also minimize inductances. They conflict of course, smaller trace has lower capacitance but higher inductance.

We use Altium for layout and have used ADS for parasitic extraction. But we cannot afford the license.

Is there a low cost alternative that is ok in terms of amount of time to get it done?

I was thinking maybe somebody has made a tool, maybe even excel, that could import the trace and image plane /traces to do a finite element analysis /model.

Any hints?

The Saturn software does the basics for standard trace geometries.

Sonnet Lite does 2.5-D em analysis for free.

Thanks, that looks quite nice.


A switcher should be small enough that the speed of light is
inconsequential. How high a frequncy did you have in mind?


It\'s not a standard switcher

Operating at 100MHz, and with 1ns switch node rise time. So even
laminate loss is important.



Sounds like fun. GaN?

Yes, EPC GaN.

One problem we encounter is driving laser diodes fast. At 5 amps per
ns, it gets hard to wire things up. Eveny nH of inductance drops 5
volts. Tx line impedances need to be a fraction of an ohm. Most laser
diode makers don\'t seem to understand this and sure don\'t furnish IBIS
files. The laser physics can help, or hurt, and that\'s not specified.

Excactly what we are looking into also. The layout did a mistake, and we
are fixing it.

Driving Pockels Cells can have similar issues, but kilovolts.

A proper sim, device and package models, Spice, IBIS, 3D e/m sim,
thermals, PCB, is probably impossible, or would take years and
megabucks. I use instinct and Dremels.

We have used ADS so far, but no more license.

If you crowd parts to keep the electricals tight, then they get hot.
Yet another dimension in the optimization space.

The power we have is low, so we pack it very tight.

 

[Klaus Vestergaard Kragelund]

On 07-01-2023 17:31, John Larkin wrote:

On Sat, 7 Jan 2023 15:37:20 +0100, Klaus Vestergaard Kragelund
klauskvik@hotmail.com> wrote:

On 07-01-2023 13:56, John Larkin wrote:
On Sat, 07 Jan 2023 02:29:48 +0100, Klaus Kragelund
klauskvik@hotmail.com> wrote:

Hi

I am working on a high frequency design in which we in principle is using a very high frequency switch mode converter

I need low loss, so need to minimize capacitive parasitics, and also minimize inductances. They conflict of course, smaller trace has lower capacitance but higher inductance.

We use Altium for layout and have used ADS for parasitic extraction. But we cannot afford the license.

Is there a low cost alternative that is ok in terms of amount of time to get it done?

I was thinking maybe somebody has made a tool, maybe even excel, that could import the trace and image plane /traces to do a finite element analysis /model.

Any hints?

The Saturn software does the basics for standard trace geometries.

Sonnet Lite does 2.5-D em analysis for free.

Thanks, that looks quite nice.


A switcher should be small enough that the speed of light is
inconsequential. How high a frequncy did you have in mind?


It\'s not a standard switcher

Operating at 100MHz, and with 1ns switch node rise time. So even
laminate loss is important.



Sounds like fun. GaN?

Yes, EPC GaN.

One problem we encounter is driving laser diodes fast. At 5 amps per
ns, it gets hard to wire things up. Eveny nH of inductance drops 5
volts. Tx line impedances need to be a fraction of an ohm. Most laser
diode makers don\'t seem to understand this and sure don\'t furnish IBIS
files. The laser physics can help, or hurt, and that\'s not specified.

Excactly what we are looking into also. The layout did a mistake, and we
are fixing it.

Driving Pockels Cells can have similar issues, but kilovolts.

A proper sim, device and package models, Spice, IBIS, 3D e/m sim,
thermals, PCB, is probably impossible, or would take years and
megabucks. I use instinct and Dremels.

We have used ADS so far, but no more license.

If you crowd parts to keep the electricals tight, then they get hot.
Yet another dimension in the optimization space.

The power we have is low, so we pack it very tight.

 

[Klaus Vestergaard Kragelund]

On 07-01-2023 20:57, John May wrote:

On Saturday, January 7, 2023 at 1:29:58 AM UTC, Klaus Kragelund wrote:
Hi

I am working on a high frequency design in which we in principle is using a very high frequency switch mode converter

I need low loss, so need to minimize capacitive parasitics, and also minimize inductances. They conflict of course, smaller trace has lower capacitance but higher inductance.

We use Altium for layout and have used ADS for parasitic extraction. But we cannot afford the license.

Is there a low cost alternative that is ok in terms of amount of time to get it done?

I was thinking maybe somebody has made a tool, maybe even excel, that could import the trace and image plane /traces to do a finite element analysis /model.

Any hints?

--
Klaus

OpenEMS - full 3D. Don\'t let the cost (£0) fool you, it\'ll give the same results as the mid 5 figure commercial offerings.

Thanks, I will check that out.

 

[Klaus Vestergaard Kragelund]

On 07-01-2023 20:57, John May wrote:

On Saturday, January 7, 2023 at 1:29:58 AM UTC, Klaus Kragelund wrote:
Hi

I am working on a high frequency design in which we in principle is using a very high frequency switch mode converter

I need low loss, so need to minimize capacitive parasitics, and also minimize inductances. They conflict of course, smaller trace has lower capacitance but higher inductance.

We use Altium for layout and have used ADS for parasitic extraction. But we cannot afford the license.

Is there a low cost alternative that is ok in terms of amount of time to get it done?

I was thinking maybe somebody has made a tool, maybe even excel, that could import the trace and image plane /traces to do a finite element analysis /model.

Any hints?

--
Klaus

OpenEMS - full 3D. Don\'t let the cost (£0) fool you, it\'ll give the same results as the mid 5 figure commercial offerings.

Thanks, I will check that out.

 

[Klaus Vestergaard Kragelund]

On 07-01-2023 20:57, John May wrote:

On Saturday, January 7, 2023 at 1:29:58 AM UTC, Klaus Kragelund wrote:
Hi

I am working on a high frequency design in which we in principle is using a very high frequency switch mode converter

I need low loss, so need to minimize capacitive parasitics, and also minimize inductances. They conflict of course, smaller trace has lower capacitance but higher inductance.

We use Altium for layout and have used ADS for parasitic extraction. But we cannot afford the license.

Is there a low cost alternative that is ok in terms of amount of time to get it done?

I was thinking maybe somebody has made a tool, maybe even excel, that could import the trace and image plane /traces to do a finite element analysis /model.

Any hints?

--
Klaus

OpenEMS - full 3D. Don\'t let the cost (£0) fool you, it\'ll give the same results as the mid 5 figure commercial offerings.

Thanks, I will check that out.

 

[John Larkin]

On Sun, 8 Jan 2023 00:31:05 +0100, Klaus Vestergaard Kragelund
<klauskvik@hotmail.com> wrote:

On 07-01-2023 17:31, John Larkin wrote:
On Sat, 7 Jan 2023 15:37:20 +0100, Klaus Vestergaard Kragelund
klauskvik@hotmail.com> wrote:

On 07-01-2023 13:56, John Larkin wrote:
On Sat, 07 Jan 2023 02:29:48 +0100, Klaus Kragelund
klauskvik@hotmail.com> wrote:

Hi

I am working on a high frequency design in which we in principle is using a very high frequency switch mode converter

I need low loss, so need to minimize capacitive parasitics, and also minimize inductances. They conflict of course, smaller trace has lower capacitance but higher inductance.

We use Altium for layout and have used ADS for parasitic extraction. But we cannot afford the license.

Is there a low cost alternative that is ok in terms of amount of time to get it done?

I was thinking maybe somebody has made a tool, maybe even excel, that could import the trace and image plane /traces to do a finite element analysis /model.

Any hints?

The Saturn software does the basics for standard trace geometries.

Sonnet Lite does 2.5-D em analysis for free.

Thanks, that looks quite nice.


A switcher should be small enough that the speed of light is
inconsequential. How high a frequncy did you have in mind?


It\'s not a standard switcher

Operating at 100MHz, and with 1ns switch node rise time. So even
laminate loss is important.



Sounds like fun. GaN?

Yes, EPC GaN.

I love those parts electrically, but they are fragile and close to
impossible to rework. I have a pulse generator output stage design
that\'s great, way better than possible with mosfets, but we did it as
throw-away baby boards to make rework possible. We build, test, and
glob-top the baby boards.

https://www.dropbox.com/s/t1whjfnrtkn2ucx/T577s_P500D.jpg?raw=1

https://www.dropbox.com/s/gm830tkb06b0mz8/T577_50v_pulse.JPG?raw=1

That pulse is lowpass filtered for beauty. The unfiltered pulse is
faster but a little ratty looking.

I used the tiny 4-ball parts, which fracture or break off the board if
they are touched. The bigger ones with fat rectangular contacts are
tougher, but the corners will still fracture if tapped.

One problem we encounter is driving laser diodes fast. At 5 amps per
ns, it gets hard to wire things up. Eveny nH of inductance drops 5
volts. Tx line impedances need to be a fraction of an ohm. Most laser
diode makers don\'t seem to understand this and sure don\'t furnish IBIS
files. The laser physics can help, or hurt, and that\'s not specified.


Excactly what we are looking into also. The layout did a mistake, and we
are fixing it.

Driving Pockels Cells can have similar issues, but kilovolts.

A proper sim, device and package models, Spice, IBIS, 3D e/m sim,
thermals, PCB, is probably impossible, or would take years and
megabucks. I use instinct and Dremels.


We have used ADS so far, but no more license.

If you crowd parts to keep the electricals tight, then they get hot.
Yet another dimension in the optimization space.


The power we have is low, so we pack it very tight.

 

[John Larkin]

On Sun, 8 Jan 2023 00:31:05 +0100, Klaus Vestergaard Kragelund
<klauskvik@hotmail.com> wrote:

On 07-01-2023 17:31, John Larkin wrote:
On Sat, 7 Jan 2023 15:37:20 +0100, Klaus Vestergaard Kragelund
klauskvik@hotmail.com> wrote:

On 07-01-2023 13:56, John Larkin wrote:
On Sat, 07 Jan 2023 02:29:48 +0100, Klaus Kragelund
klauskvik@hotmail.com> wrote:

Hi

I am working on a high frequency design in which we in principle is using a very high frequency switch mode converter

I need low loss, so need to minimize capacitive parasitics, and also minimize inductances. They conflict of course, smaller trace has lower capacitance but higher inductance.

We use Altium for layout and have used ADS for parasitic extraction. But we cannot afford the license.

Is there a low cost alternative that is ok in terms of amount of time to get it done?

I was thinking maybe somebody has made a tool, maybe even excel, that could import the trace and image plane /traces to do a finite element analysis /model.

Any hints?

The Saturn software does the basics for standard trace geometries.

Sonnet Lite does 2.5-D em analysis for free.

Thanks, that looks quite nice.


A switcher should be small enough that the speed of light is
inconsequential. How high a frequncy did you have in mind?


It\'s not a standard switcher

Operating at 100MHz, and with 1ns switch node rise time. So even
laminate loss is important.



Sounds like fun. GaN?

Yes, EPC GaN.

I love those parts electrically, but they are fragile and close to
impossible to rework. I have a pulse generator output stage design
that\'s great, way better than possible with mosfets, but we did it as
throw-away baby boards to make rework possible. We build, test, and
glob-top the baby boards.

https://www.dropbox.com/s/t1whjfnrtkn2ucx/T577s_P500D.jpg?raw=1

https://www.dropbox.com/s/gm830tkb06b0mz8/T577_50v_pulse.JPG?raw=1

That pulse is lowpass filtered for beauty. The unfiltered pulse is
faster but a little ratty looking.

I used the tiny 4-ball parts, which fracture or break off the board if
they are touched. The bigger ones with fat rectangular contacts are
tougher, but the corners will still fracture if tapped.

One problem we encounter is driving laser diodes fast. At 5 amps per
ns, it gets hard to wire things up. Eveny nH of inductance drops 5
volts. Tx line impedances need to be a fraction of an ohm. Most laser
diode makers don\'t seem to understand this and sure don\'t furnish IBIS
files. The laser physics can help, or hurt, and that\'s not specified.


Excactly what we are looking into also. The layout did a mistake, and we
are fixing it.

Driving Pockels Cells can have similar issues, but kilovolts.

A proper sim, device and package models, Spice, IBIS, 3D e/m sim,
thermals, PCB, is probably impossible, or would take years and
megabucks. I use instinct and Dremels.


We have used ADS so far, but no more license.

If you crowd parts to keep the electricals tight, then they get hot.
Yet another dimension in the optimization space.


The power we have is low, so we pack it very tight.

 

[John Larkin]

On Sun, 8 Jan 2023 00:31:05 +0100, Klaus Vestergaard Kragelund
<klauskvik@hotmail.com> wrote:

On 07-01-2023 17:31, John Larkin wrote:
On Sat, 7 Jan 2023 15:37:20 +0100, Klaus Vestergaard Kragelund
klauskvik@hotmail.com> wrote:

On 07-01-2023 13:56, John Larkin wrote:
On Sat, 07 Jan 2023 02:29:48 +0100, Klaus Kragelund
klauskvik@hotmail.com> wrote:

Hi

I am working on a high frequency design in which we in principle is using a very high frequency switch mode converter

I need low loss, so need to minimize capacitive parasitics, and also minimize inductances. They conflict of course, smaller trace has lower capacitance but higher inductance.

We use Altium for layout and have used ADS for parasitic extraction. But we cannot afford the license.

Is there a low cost alternative that is ok in terms of amount of time to get it done?

I was thinking maybe somebody has made a tool, maybe even excel, that could import the trace and image plane /traces to do a finite element analysis /model.

Any hints?

The Saturn software does the basics for standard trace geometries.

Sonnet Lite does 2.5-D em analysis for free.

Thanks, that looks quite nice.


A switcher should be small enough that the speed of light is
inconsequential. How high a frequncy did you have in mind?


It\'s not a standard switcher

Operating at 100MHz, and with 1ns switch node rise time. So even
laminate loss is important.



Sounds like fun. GaN?

Yes, EPC GaN.

I love those parts electrically, but they are fragile and close to
impossible to rework. I have a pulse generator output stage design
that\'s great, way better than possible with mosfets, but we did it as
throw-away baby boards to make rework possible. We build, test, and
glob-top the baby boards.

https://www.dropbox.com/s/t1whjfnrtkn2ucx/T577s_P500D.jpg?raw=1

https://www.dropbox.com/s/gm830tkb06b0mz8/T577_50v_pulse.JPG?raw=1

That pulse is lowpass filtered for beauty. The unfiltered pulse is
faster but a little ratty looking.

I used the tiny 4-ball parts, which fracture or break off the board if
they are touched. The bigger ones with fat rectangular contacts are
tougher, but the corners will still fracture if tapped.

One problem we encounter is driving laser diodes fast. At 5 amps per
ns, it gets hard to wire things up. Eveny nH of inductance drops 5
volts. Tx line impedances need to be a fraction of an ohm. Most laser
diode makers don\'t seem to understand this and sure don\'t furnish IBIS
files. The laser physics can help, or hurt, and that\'s not specified.


Excactly what we are looking into also. The layout did a mistake, and we
are fixing it.

Driving Pockels Cells can have similar issues, but kilovolts.

A proper sim, device and package models, Spice, IBIS, 3D e/m sim,
thermals, PCB, is probably impossible, or would take years and
megabucks. I use instinct and Dremels.


We have used ADS so far, but no more license.

If you crowd parts to keep the electricals tight, then they get hot.
Yet another dimension in the optimization space.


The power we have is low, so we pack it very tight.

 

[Klaus Vestergaard Kragelund]

On 07-01-2023 13:56, John Larkin wrote:

On Sat, 07 Jan 2023 02:29:48 +0100, Klaus Kragelund
klauskvik@hotmail.com> wrote:

Hi

I am working on a high frequency design in which we in principle is using a very high frequency switch mode converter

I need low loss, so need to minimize capacitive parasitics, and also minimize inductances. They conflict of course, smaller trace has lower capacitance but higher inductance.

We use Altium for layout and have used ADS for parasitic extraction. But we cannot afford the license.

Is there a low cost alternative that is ok in terms of amount of time to get it done?

I was thinking maybe somebody has made a tool, maybe even excel, that could import the trace and image plane /traces to do a finite element analysis /model.

Any hints?

The Saturn software does the basics for standard trace geometries.

Sonnet Lite does 2.5-D em analysis for free.

Thanks, that looks quite nice.

A switcher should be small enough that the speed of light is
inconsequential. How high a frequncy did you have in mind?

It\'s not a standard switcher

Operating at 100MHz, and with 1ns switch node rise time. So even
laminate loss is important.

 

[Klaus Vestergaard Kragelund]

On 07-01-2023 13:56, John Larkin wrote:

On Sat, 07 Jan 2023 02:29:48 +0100, Klaus Kragelund
klauskvik@hotmail.com> wrote:

Hi

I am working on a high frequency design in which we in principle is using a very high frequency switch mode converter

I need low loss, so need to minimize capacitive parasitics, and also minimize inductances. They conflict of course, smaller trace has lower capacitance but higher inductance.

We use Altium for layout and have used ADS for parasitic extraction. But we cannot afford the license.

Is there a low cost alternative that is ok in terms of amount of time to get it done?

I was thinking maybe somebody has made a tool, maybe even excel, that could import the trace and image plane /traces to do a finite element analysis /model.

Any hints?

The Saturn software does the basics for standard trace geometries.

Sonnet Lite does 2.5-D em analysis for free.

Thanks, that looks quite nice.

A switcher should be small enough that the speed of light is
inconsequential. How high a frequncy did you have in mind?

It\'s not a standard switcher

Operating at 100MHz, and with 1ns switch node rise time. So even
laminate loss is important.

 

[Klaus Vestergaard Kragelund]

On 07-01-2023 13:56, John Larkin wrote:

On Sat, 07 Jan 2023 02:29:48 +0100, Klaus Kragelund
klauskvik@hotmail.com> wrote:

Hi

I am working on a high frequency design in which we in principle is using a very high frequency switch mode converter

I need low loss, so need to minimize capacitive parasitics, and also minimize inductances. They conflict of course, smaller trace has lower capacitance but higher inductance.

We use Altium for layout and have used ADS for parasitic extraction. But we cannot afford the license.

Is there a low cost alternative that is ok in terms of amount of time to get it done?

I was thinking maybe somebody has made a tool, maybe even excel, that could import the trace and image plane /traces to do a finite element analysis /model.

Any hints?

The Saturn software does the basics for standard trace geometries.

Sonnet Lite does 2.5-D em analysis for free.

Thanks, that looks quite nice.

A switcher should be small enough that the speed of light is
inconsequential. How high a frequncy did you have in mind?

It\'s not a standard switcher

Operating at 100MHz, and with 1ns switch node rise time. So even
laminate loss is important.

 

[John Larkin]

On Sat, 7 Jan 2023 15:37:20 +0100, Klaus Vestergaard Kragelund
<klauskvik@hotmail.com> wrote:

On 07-01-2023 13:56, John Larkin wrote:
On Sat, 07 Jan 2023 02:29:48 +0100, Klaus Kragelund
klauskvik@hotmail.com> wrote:

Hi

I am working on a high frequency design in which we in principle is using a very high frequency switch mode converter

I need low loss, so need to minimize capacitive parasitics, and also minimize inductances. They conflict of course, smaller trace has lower capacitance but higher inductance.

We use Altium for layout and have used ADS for parasitic extraction. But we cannot afford the license.

Is there a low cost alternative that is ok in terms of amount of time to get it done?

I was thinking maybe somebody has made a tool, maybe even excel, that could import the trace and image plane /traces to do a finite element analysis /model.

Any hints?

The Saturn software does the basics for standard trace geometries.

Sonnet Lite does 2.5-D em analysis for free.

Thanks, that looks quite nice.


A switcher should be small enough that the speed of light is
inconsequential. How high a frequncy did you have in mind?


It\'s not a standard switcher

Operating at 100MHz, and with 1ns switch node rise time. So even
laminate loss is important.

Sounds like fun. GaN?

One problem we encounter is driving laser diodes fast. At 5 amps per
ns, it gets hard to wire things up. Eveny nH of inductance drops 5
volts. Tx line impedances need to be a fraction of an ohm. Most laser
diode makers don\'t seem to understand this and sure don\'t furnish IBIS
files. The laser physics can help, or hurt, and that\'s not specified.

Driving Pockels Cells can have similar issues, but kilovolts.

A proper sim, device and package models, Spice, IBIS, 3D e/m sim,
thermals, PCB, is probably impossible, or would take years and
megabucks. I use instinct and Dremels.

If you crowd parts to keep the electricals tight, then they get hot.
Yet another dimension in the optimization space.

 

[John Larkin]

On Sat, 7 Jan 2023 15:37:20 +0100, Klaus Vestergaard Kragelund
<klauskvik@hotmail.com> wrote:

On 07-01-2023 13:56, John Larkin wrote:
On Sat, 07 Jan 2023 02:29:48 +0100, Klaus Kragelund
klauskvik@hotmail.com> wrote:

Hi

I am working on a high frequency design in which we in principle is using a very high frequency switch mode converter

I need low loss, so need to minimize capacitive parasitics, and also minimize inductances. They conflict of course, smaller trace has lower capacitance but higher inductance.

We use Altium for layout and have used ADS for parasitic extraction. But we cannot afford the license.

Is there a low cost alternative that is ok in terms of amount of time to get it done?

I was thinking maybe somebody has made a tool, maybe even excel, that could import the trace and image plane /traces to do a finite element analysis /model.

Any hints?

The Saturn software does the basics for standard trace geometries.

Sonnet Lite does 2.5-D em analysis for free.

Thanks, that looks quite nice.


A switcher should be small enough that the speed of light is
inconsequential. How high a frequncy did you have in mind?


It\'s not a standard switcher

Operating at 100MHz, and with 1ns switch node rise time. So even
laminate loss is important.

Sounds like fun. GaN?

One problem we encounter is driving laser diodes fast. At 5 amps per
ns, it gets hard to wire things up. Eveny nH of inductance drops 5
volts. Tx line impedances need to be a fraction of an ohm. Most laser
diode makers don\'t seem to understand this and sure don\'t furnish IBIS
files. The laser physics can help, or hurt, and that\'s not specified.

Driving Pockels Cells can have similar issues, but kilovolts.

A proper sim, device and package models, Spice, IBIS, 3D e/m sim,
thermals, PCB, is probably impossible, or would take years and
megabucks. I use instinct and Dremels.

If you crowd parts to keep the electricals tight, then they get hot.
Yet another dimension in the optimization space.