Extraction of nfet and pfet

  • Thread starter dati_remo@libero.it
  • Start date
D

dati_remo@libero.it

Guest
In my divaEXT.rul is written:

(drcExtractRules
(bkgnd = (geomBkgnd))
(pdiff = (geomOr "pdiff"))
(ndiff = (geomOr "ndiff"))
(pwell = (geomOr "pwell"))
(metal1 = (geomOr "metal1"))
(metal2 = (geomOr "metal2"))
(metal3 = (geomOr "metal3"))
(metal4 = (geomOr "metal4"))
(cont = (geomOr "contact"))
(poly = (geomOr "poly"))
(pgate = (geomAnd poly pdiff))
(ngate = (geomAnd poly ndiff))
(nsd = (geomAndNot ndiff ngate))
(psd = (geomAndNot pdiff pgate))
(via = (geomOr "v1"))
(via1 = (geomOr "v2"))
(via2 = (geomOr "v3"))
(Ptap = (geomAnd psd pwell))
(Ntap = (geomAndNot nsd pwell))
(sub = (geomAndNot bkgnd pwell

...........
...........

(switch "extract") then
(extractDevice pgate
(poly "G")
(psd "S" "D")
(sub "B")
"pfet ivpcell"
)

(extractDevice ngate
(poly "G")
(nsd "S" "D")
(pwell "B")
"nfet ivpcell"
)

but I can't extract those components, I can only extract capacitors.

Someone can help me?

Thanks
 
Did you set the extract switch? If you did, what does the log show when
those rules are executed? Anything about bad formed shapes? You have
provided very little to work with here.

On 11 Feb 2004 08:27:45 -0800, dati_remo@libero.it (dati_remo@libero.it)
wrote:

In my divaEXT.rul is written:

(drcExtractRules
(bkgnd = (geomBkgnd))
(pdiff = (geomOr "pdiff"))
(ndiff = (geomOr "ndiff"))
(pwell = (geomOr "pwell"))
(metal1 = (geomOr "metal1"))
(metal2 = (geomOr "metal2"))
(metal3 = (geomOr "metal3"))
(metal4 = (geomOr "metal4"))
(cont = (geomOr "contact"))
(poly = (geomOr "poly"))
(pgate = (geomAnd poly pdiff))
(ngate = (geomAnd poly ndiff))
(nsd = (geomAndNot ndiff ngate))
(psd = (geomAndNot pdiff pgate))
(via = (geomOr "v1"))
(via1 = (geomOr "v2"))
(via2 = (geomOr "v3"))
(Ptap = (geomAnd psd pwell))
(Ntap = (geomAndNot nsd pwell))
(sub = (geomAndNot bkgnd pwell

...........
...........

(switch "extract") then
(extractDevice pgate
(poly "G")
(psd "S" "D")
(sub "B")
"pfet ivpcell"
)

(extractDevice ngate
(poly "G")
(nsd "S" "D")
(pwell "B")
"nfet ivpcell"
)

but I can't extract those components, I can only extract capacitors.

Someone can help me?

Thanks
Click to expand...
 
Yes, I did it.

This is the log file of the extraction operation.

Thank you



\a setExtForm()
\p >
\a hiFormDone(ivExtOptionsForm)
\o
\o Extraction started at Fri Feb 13 12:38:51 2004
\o
\o
\o library: FF_NO_LEAK
\o cell: VGND_FF_BALL_2
\o view: layout
\o Rules source is a simple file.
\o Rules path is /home/remol/WORK_CADENCE/divaEXT2.rul.
\o Inclusion limit is set to 1000.
\o Switches used: extract.
\o Running layout extraction analysis
\o flat mode
\o Full checking.
\o 50 pcapacitor parasitics created.
\o 0 pcapacitor parasitics created.
\o 0 pcapacitor parasitics created.
\o saving rep FF_NO_LEAK/VGND_FF_BALL_2/extracted
\o Extraction started.......Fri Feb 13 12:38:51 2004
\o completed ....Fri Feb 13 12:38:52 2004
\o CPU TIME = 00:00:00 TOTAL TIME = 00:00:01
\o ********* Summary of rule violation for cell "VGND_FF_BALL_2
layout" *********
\o
\o Total errors found: 0




Diva Physical Verification <diva@cadence.com> wrote in message news:<i8sl20lbpig9p6s4fnr58oogbs09s6kr35@4ax.com>...
Did you set the extract switch? If you did, what does the log show when
those rules are executed? Anything about bad formed shapes? You have
provided very little to work with here.

On 11 Feb 2004 08:27:45 -0800, dati_remo@libero.it (dati_remo@libero.it)
wrote:

In my divaEXT.rul is written:

(drcExtractRules
(bkgnd = (geomBkgnd))
(pdiff = (geomOr "pdiff"))
(ndiff = (geomOr "ndiff"))
(pwell = (geomOr "pwell"))
(metal1 = (geomOr "metal1"))
(metal2 = (geomOr "metal2"))
(metal3 = (geomOr "metal3"))
(metal4 = (geomOr "metal4"))
(cont = (geomOr "contact"))
(poly = (geomOr "poly"))
(pgate = (geomAnd poly pdiff))
(ngate = (geomAnd poly ndiff))
(nsd = (geomAndNot ndiff ngate))
(psd = (geomAndNot pdiff pgate))
(via = (geomOr "v1"))
(via1 = (geomOr "v2"))
(via2 = (geomOr "v3"))
(Ptap = (geomAnd psd pwell))
(Ntap = (geomAndNot nsd pwell))
(sub = (geomAndNot bkgnd pwell

...........
...........

(switch "extract") then
(extractDevice pgate
(poly "G")
(psd "S" "D")
(sub "B")
"pfet ivpcell"
)

(extractDevice ngate
(poly "G")
(nsd "S" "D")
(pwell "B")
"nfet ivpcell"
)

but I can't extract those components, I can only extract capacitors.

Someone can help me?

Thanks
Click to expand...
 
What means this error?

\o error: Layer 'sub_pippo_SD' must be connected.

Tahnks


o Extraction started at Fri Feb 13 15:58:09 2004
\o
\o
\o library: FF_NO_LEAK
\o cell: nhsmos4
\o view: layoutXL
\o Rules source is a simple file.
\o Rules path is /home/remol/WORK_CADENCE/divaEXT2.rul.
\o Inclusion limit is set to 1000.
\o Switches used: extract.
\o Parsing drcExtractRules of
"/home/remol/WORK_CADENCE/divaEXT2.rul"...
\o error: Layer 'sub_pippo_SD' must be connected.
\o error: Layer 'sub_pippo1' must be connected.
\o 81. extractDevice(ngate (poly "G") (sub_pippo_SD "S" "D")
(sub_pippo1 "B") "nfet ivpcell")
\o error: The saveRecognition() command must appear after
extractDevice()
\o or extractMOS() command and the first argument must be a device
recognition layer.
\o 105. saveRecognition(pgate "poly")
\o info: If short location check is desired later on, check the
saveInterconnect
\o statement for correctness:
\o Interconnect layer via, cont, psd, nsd, via1, via2, Ptap, Ntap,
sub not saved.
\o
\o Errors exist in the rules file
"/home/remol/WORK_CADENCE/divaEXT2.rul".
\o Verification program terminated.
 
that means there must be a geomConnect() or geomStamp()
statement for this layer.

<dati_remo@libero.it> wrote in message
news:eddc78be.0402130703.c5082c@posting.google.com...
What means this error?

\o error: Layer 'sub_pippo_SD' must be connected.

Tahnks


o Extraction started at Fri Feb 13 15:58:09 2004
\o
\o
\o library: FF_NO_LEAK
\o cell: nhsmos4
\o view: layoutXL
\o Rules source is a simple file.
\o Rules path is /home/remol/WORK_CADENCE/divaEXT2.rul.
\o Inclusion limit is set to 1000.
\o Switches used: extract.
\o Parsing drcExtractRules of
"/home/remol/WORK_CADENCE/divaEXT2.rul"...
\o error: Layer 'sub_pippo_SD' must be connected.
\o error: Layer 'sub_pippo1' must be connected.
\o 81. extractDevice(ngate (poly "G") (sub_pippo_SD "S" "D")
(sub_pippo1 "B") "nfet ivpcell")
\o error: The saveRecognition() command must appear after
extractDevice()
\o or extractMOS() command and the first argument must be a device
recognition layer.
\o 105. saveRecognition(pgate "poly")
\o info: If short location check is desired later on, check the
saveInterconnect
\o statement for correctness:
\o Interconnect layer via, cont, psd, nsd, via1, via2, Ptap, Ntap,
sub not saved.
\o
\o Errors exist in the rules file
"/home/remol/WORK_CADENCE/divaEXT2.rul".
\o Verification program terminated.
Click to expand...
 
Or that it is derived from a layer that is in geomConnect() or geomStamp()
using something "reducing" like geomAnd() which inherits the connectivity
(geomAnd will always return a subset of the original layer - and so is
"reducing" - geomOr() will however expand the original layer, and so
doesn't transfer connectivity).

Andrew.

On Fri, 13 Feb 2004 16:33:37 +0100, "S. Badel" <stephane.badel@epfl.ch> wrote:

that means there must be a geomConnect() or geomStamp()
statement for this layer.

dati_remo@libero.it> wrote in message
news:eddc78be.0402130703.c5082c@posting.google.com...
What means this error?

\o error: Layer 'sub_pippo_SD' must be connected.

Tahnks


o Extraction started at Fri Feb 13 15:58:09 2004
\o
\o
\o library: FF_NO_LEAK
\o cell: nhsmos4
\o view: layoutXL
\o Rules source is a simple file.
\o Rules path is /home/remol/WORK_CADENCE/divaEXT2.rul.
\o Inclusion limit is set to 1000.
\o Switches used: extract.
\o Parsing drcExtractRules of
"/home/remol/WORK_CADENCE/divaEXT2.rul"...
\o error: Layer 'sub_pippo_SD' must be connected.
\o error: Layer 'sub_pippo1' must be connected.
\o 81. extractDevice(ngate (poly "G") (sub_pippo_SD "S" "D")
(sub_pippo1 "B") "nfet ivpcell")
\o error: The saveRecognition() command must appear after
extractDevice()
\o or extractMOS() command and the first argument must be a device
recognition layer.
\o 105. saveRecognition(pgate "poly")
\o info: If short location check is desired later on, check the
saveInterconnect
\o statement for correctness:
\o Interconnect layer via, cont, psd, nsd, via1, via2, Ptap, Ntap,
sub not saved.
\o
\o Errors exist in the rules file
"/home/remol/WORK_CADENCE/divaEXT2.rul".
\o Verification program terminated.
Click to expand...
--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd
 
With this divaEXT.rul file I can't extract the transistor of the
layout.


(drcExtractRules
(bkgnd = (geomBkgnd))
(pdiff = (geomOr "pdiff"))
(ndiff = (geomOr "ndiff"))
(pwell = (geomOr "pwell"))
(metal1 = (geomOr "metal1"))
(metal2 = (geomOr "metal2"))
(metal3 = (geomOr "metal3"))
(metal4 = (geomOr "metal4"))
(cont = (geomOr "contact"))
(poly = (geomOr "poly"))

(adlvtn = (geomOr "adlvtn"))
(nplus = (geomOr "nplus"))
(active = (geomOr "active"))

(sub_1 = (geomAnd adlvtn nplus))
(sub__SD = (geomAnd sub_1 active))
(sub__SD_2 = (geomAndNot sub__SD poly))
(sub__SD_3 = (geomAnd sub__SD_2 sub__SD))
(sub_1_2 = (geomAndNot bkgnd sub__SD))

(pgate = (geomAnd poly pdiff))
(ngate = (geomAnd poly ndiff))
(nsd = (geomAndNot ndiff ngate))
(psd = (geomAndNot pdiff pgate))
(via = (geomOr "v1"))
(via1 = (geomOr "v2"))
(via2 = (geomOr "v3"))
(Ptap = (geomAnd psd pwell))
(Ntap = (geomAndNot nsd pwell))
(sub = (geomAndNot bkgnd pwell))

(ivIf
(switch "do_pre") then
(measureResistance poly "lrescap" 25 0.56
"r"
(cap "c"
((1.6e-17 * a) + (2.8e-18 * p))
)
(ignore <= 0.05)
(save "y1")
(contact cont 0.03 0.5)
)
)


(ivIf
(switch "drc?") then
(drc pwell
(width < 1.8) "Minimum P- width = 1.8"
)
;;(drc pwell
;; (sep < 4.2) diffNet "P- to P- spacing = 4.2"
;;)
(drc nsd psd
(sep < 0.9) diffNet
"Ndiff to Pdiff on different nets = 0.9"
)
(badPdiff = (geomStraddle psd pwell))
(saveDerived badPdiff "Pdiff straddling Pwell")
(drc nsd pwell
(sep < 0.6) "Ndiff (substrate contact) to P-well = 0.6"
)
(drc pwell nsd
(enc < 0.6) "Ndiff (inside P-well) to P-well edge = 0.6"
)
(diffusion = (geomOr pdiff ndiff))
(drc diffusion
(width < 0.6) "Minimum Source/Drain interconnect width = 0.6"
)
(drc diffusion
(sep < 0.6) "Minimum Source/Drain spacing = 0.6"
)
(drc poly
(width < 0.6) "Minimum poly width = 0.6"
)
(drc poly
(sep < 0.6) "Minimum poly to poly spacing = 0.6"
)
(drc poly diffusion
(enc < 0.9) "Minimum gate overlap field = 0.9"
)
(gate = (geomAnd poly diffusion))
(drc diffusion gate
((0 < enc) < 1.2) opposite
"Minimum gate to diffusion edge = 1.2"
)
(drc poly diffusion
(sep < 0.3) "Minimum poly in field to edge of diffusion = 0.3"
)
(drc pimplant psd
((0 < enc) < 0.3) "P-implant overlap of S/D = 0.3"
)
(drc pimplant nsd
((0 < sep) < 0.3) "N Diff to P-implant = 0.3"
)
(drc pimplant
(sep < 0.3) "Minimum P-implant mask spacing = 0.3"
)
(drc pimplant
(notch < 0.3) "Minimum P-implant mask spacing (notch) = 3"
)
(buttcon = (geomStraddle cont ndiff))
(badcon = (geomAndNot cont
(geomCat diffusion metal1)
))
(nTapCon = (geomInside cont Ntap))
(pTapCon = (geomInside cont Ptap))
(tapCon = (geomOr nTapCon pTapCon))
(noTapCon = (geomAndNot cont tapCon))
(saveDerived badcon "Contacts not inside diffusion or metal1 are bad
contacts")
(saveDerived buttcon "Butting contacts not allowed in this design")
(drc cont
(width < 0.6) "Minimum contact size = 0.6"
)
(drc cont
(width < 1.9)
(1.9 < length) "Maximum size of contact .9 x .9"
)
(drc cont
(4 < area) "Maximum size of contact .9 x .9"
)
(drc cont
(sep < 0.6) "Minimum contact spacing = 0.6"
)
(drc diffusion noTapCon
(enc < 0.6) "Nidff, Pidff diffusion overlap contacts = 0.6"
)
(drc diffusion tapCon
(enc < 0.3) "Nidff, Pidff diffusion overlap well tap contacts =
0.3"
)
(drc cont gate
(sep < 0.6) "Nidff, Pidff diffusion contacts to poly gate = 0.6"
)
(drc poly cont
(enc < 0.3) "poly overlap contacts = 0.3"
)
(drc metal1
(width < 0.6) "Metal width = 0.6"
)
(drc metal1
(sep < 0.6) "Metal spacing = 0.6"
)
(drc metal1 cont
(enc < 0.6) "Minimum Metal overlap contacts = 0.6"
)
(Badvia = (geomAnd via cont))
(saveDerived Badvia "Via not allowed over metal-to-diffusion
contact")
(drc via
(width < 0.6) "Minimum via opening = 2"
)
(drc via
(width < 0.9)
(0.9 < length) "Max via = .9 x .9"
)
(drc via
(0.81 < area) "Max via = .9 x .9"
)
(drc via
(sep < 1.2) "Minimum via spacing = 1.2"
)
(drc poly via
(sep < 0.3) "Via to poly = 0.3"
)
(drc cont via
(sep < 0.6) "Via to contact = 0.6"
)
(drc metal1 via
(enc < 0.6) "Metal1 overlap of via = 0.6"
)
(drc metal2
(width < 0.6) "Metal2 minimum width = 0.6"
)
(drc metal2
(sep < 0.6) "Metal2 minimum spacing = 0.6"
)
(drc metal2 via
(enc < 0.6) "Metal2 overlap via = 0.6"
)
)
(ivIf
(switch "extract") then

(geomConnect
via(via cont poly metal1 psd nsd)
via(via cont sub__SD metal1)
via(via cont sub__SD_2 metal1)
via(via cont sub__SD_3 metal1)
via(via cont sub_1 metal1)
via(via cont sub_1_2 metal1)

label("v1" metal1 metal2)
label("v1" via1 metal2 metal3)
label("v1" via2 metal3 metal4)
label("v1" Ptap pwell psd metal1)
label("v1" Ntap sub nsd metal1)

label("v1" cont sub__SD_3 metal1)

)

(extractDevice pgate
(poly "G")
(psd "S" "D")
(sub "B")
"pfet ivpcell"
)


(extractDevice ngate
(poly "G")
(sub__SD_3 "S" "D")
(sub_1_2 "B")
"nfet ivpcell"
)


(wp = (measureParameter length
(pgate coincident poly) 5e-07
))
(wn = (measureParameter length
(ngate coincident poly) 5e-07
))
(lp = (measureParameter length
(pgate inside poly) 5e-07
))
(ln = (measureParameter length
(ngate inside poly) 5e-07
))
(saveParameter lp "l")
(saveParameter ln "l")
(saveParameter wp "w")
(saveParameter wn "w")

(polymetal = (measureParasitic area
(metal1 over poly) 2.8e-16 two_net
))
(polymetal2 = (measureParasitic area
(metal2 over poly not_over metal1) 2.4e-16 two_net
))
(met2met1 = (measureParasitic area
(metal2 over metal1) 2e-16 two_net
))
(saveParasitic polymetal "PLUS" "MINUS" "c"
"pcapacitor"
)
(saveParasitic polymetal2 "PLUS" "MINUS" "c"
"pcapacitor"
)
(saveParasitic met2met1 "PLUS" "MINUS" "c"
"pcapacitor"
)
(saveRecognition ngate "poly")
(saveRecognition pgate "poly")

(saveInterconnect metal1 poly pwell metal2 metal3 metal4)

)
)





And this is the report of the extraction:



\a setExtForm()
\p >
\a hiFormDone(ivExtOptionsForm)
\o
\o Extraction started at Tue Feb 17 14:18:37 2004
\o
\o
\o library: FF_NO_LEAK
\o cell: VGND_FF_BALL_2
\o view: layout
\o Rules source is a simple file.
\o Rules path is /home/remol/WORK_CADENCE/divaEXT2_group.rul.
\o Inclusion limit is set to 1000.
\o Switches used: extract.
\o Running layout extraction analysis
\o flat mode
\o Full checking.
\o 50 pcapacitor parasitics created.
\o 0 pcapacitor parasitics created.
\o 0 pcapacitor parasitics created.
\o saving rep FF_NO_LEAK/VGND_FF_BALL_2/extracted
\o Extraction started.......Tue Feb 17 14:18:37 2004
\o completed ....Tue Feb 17 14:18:38 2004
\o CPU TIME = 00:00:00 TOTAL TIME = 00:00:01
\o ********* Summary of rule violation for cell "VGND_FF_BALL_2
layout" *********
\o
\o Total errors found: 0
\


















Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<np1q205lo0m2fovmgcfrbr5169avteitpk@4ax.com>...
Or that it is derived from a layer that is in geomConnect() or geomStamp()
using something "reducing" like geomAnd() which inherits the connectivity
(geomAnd will always return a subset of the original layer - and so is
"reducing" - geomOr() will however expand the original layer, and so
doesn't transfer connectivity).

Andrew.

On Fri, 13 Feb 2004 16:33:37 +0100, "S. Badel" <stephane.badel@epfl.ch> wrote:

that means there must be a geomConnect() or geomStamp()
statement for this layer.

dati_remo@libero.it> wrote in message
news:eddc78be.0402130703.c5082c@posting.google.com...
What means this error?

\o error: Layer 'sub_pippo_SD' must be connected.

Tahnks


o Extraction started at Fri Feb 13 15:58:09 2004
\o
\o
\o library: FF_NO_LEAK
\o cell: nhsmos4
\o view: layoutXL
\o Rules source is a simple file.
\o Rules path is /home/remol/WORK_CADENCE/divaEXT2.rul.
\o Inclusion limit is set to 1000.
\o Switches used: extract.
\o Parsing drcExtractRules of
"/home/remol/WORK_CADENCE/divaEXT2.rul"...
\o error: Layer 'sub_pippo_SD' must be connected.
\o error: Layer 'sub_pippo1' must be connected.
\o 81. extractDevice(ngate (poly "G") (sub_pippo_SD "S" "D")
(sub_pippo1 "B") "nfet ivpcell")
\o error: The saveRecognition() command must appear after
extractDevice()
\o or extractMOS() command and the first argument must be a device
recognition layer.
\o 105. saveRecognition(pgate "poly")
\o info: If short location check is desired later on, check the
saveInterconnect
\o statement for correctness:
\o Interconnect layer via, cont, psd, nsd, via1, via2, Ptap, Ntap,
sub not saved.
\o
\o Errors exist in the rules file
"/home/remol/WORK_CADENCE/divaEXT2.rul".
\o Verification program terminated.
Click to expand...
 
your via statements look weird.
should probably be something more like

via(cont poly metal1 psd nsd)
via(cont sub__SD metal1)
via(cont sub__SD_2 metal1)
via(cont sub__SD_3 metal1)
via(cont sub_1 metal1)
via(cont sub_1_2 metal1)
via( via metal1 metal2 )
via( via1 metal2 metal3 )
via( via2 metal3 metal4 )

label statements also look weird to me.
try removing them.


<dati_remo@libero.it> wrote in message
news:eddc78be.0402170524.2a4d84f5@posting.google.com...
With this divaEXT.rul file I can't extract the transistor of the
layout.


(drcExtractRules
(bkgnd = (geomBkgnd))
(pdiff = (geomOr "pdiff"))
(ndiff = (geomOr "ndiff"))
(pwell = (geomOr "pwell"))
(metal1 = (geomOr "metal1"))
(metal2 = (geomOr "metal2"))
(metal3 = (geomOr "metal3"))
(metal4 = (geomOr "metal4"))
(cont = (geomOr "contact"))
(poly = (geomOr "poly"))

(adlvtn = (geomOr "adlvtn"))
(nplus = (geomOr "nplus"))
(active = (geomOr "active"))

(sub_1 = (geomAnd adlvtn nplus))
(sub__SD = (geomAnd sub_1 active))
(sub__SD_2 = (geomAndNot sub__SD poly))
(sub__SD_3 = (geomAnd sub__SD_2 sub__SD))
(sub_1_2 = (geomAndNot bkgnd sub__SD))

(pgate = (geomAnd poly pdiff))
(ngate = (geomAnd poly ndiff))
(nsd = (geomAndNot ndiff ngate))
(psd = (geomAndNot pdiff pgate))
(via = (geomOr "v1"))
(via1 = (geomOr "v2"))
(via2 = (geomOr "v3"))
(Ptap = (geomAnd psd pwell))
(Ntap = (geomAndNot nsd pwell))
(sub = (geomAndNot bkgnd pwell))

(ivIf
(switch "do_pre") then
(measureResistance poly "lrescap" 25 0.56
"r"
(cap "c"
((1.6e-17 * a) + (2.8e-18 * p))
)
(ignore <= 0.05)
(save "y1")
(contact cont 0.03 0.5)
)
)


(ivIf
(switch "drc?") then
(drc pwell
(width < 1.8) "Minimum P- width = 1.8"
)
;;(drc pwell
;; (sep < 4.2) diffNet "P- to P- spacing = 4.2"
;;)
(drc nsd psd
(sep < 0.9) diffNet
"Ndiff to Pdiff on different nets = 0.9"
)
(badPdiff = (geomStraddle psd pwell))
(saveDerived badPdiff "Pdiff straddling Pwell")
(drc nsd pwell
(sep < 0.6) "Ndiff (substrate contact) to P-well = 0.6"
)
(drc pwell nsd
(enc < 0.6) "Ndiff (inside P-well) to P-well edge = 0.6"
)
(diffusion = (geomOr pdiff ndiff))
(drc diffusion
(width < 0.6) "Minimum Source/Drain interconnect width = 0.6"
)
(drc diffusion
(sep < 0.6) "Minimum Source/Drain spacing = 0.6"
)
(drc poly
(width < 0.6) "Minimum poly width = 0.6"
)
(drc poly
(sep < 0.6) "Minimum poly to poly spacing = 0.6"
)
(drc poly diffusion
(enc < 0.9) "Minimum gate overlap field = 0.9"
)
(gate = (geomAnd poly diffusion))
(drc diffusion gate
((0 < enc) < 1.2) opposite
"Minimum gate to diffusion edge = 1.2"
)
(drc poly diffusion
(sep < 0.3) "Minimum poly in field to edge of diffusion = 0.3"
)
(drc pimplant psd
((0 < enc) < 0.3) "P-implant overlap of S/D = 0.3"
)
(drc pimplant nsd
((0 < sep) < 0.3) "N Diff to P-implant = 0.3"
)
(drc pimplant
(sep < 0.3) "Minimum P-implant mask spacing = 0.3"
)
(drc pimplant
(notch < 0.3) "Minimum P-implant mask spacing (notch) = 3"
)
(buttcon = (geomStraddle cont ndiff))
(badcon = (geomAndNot cont
(geomCat diffusion metal1)
))
(nTapCon = (geomInside cont Ntap))
(pTapCon = (geomInside cont Ptap))
(tapCon = (geomOr nTapCon pTapCon))
(noTapCon = (geomAndNot cont tapCon))
(saveDerived badcon "Contacts not inside diffusion or metal1 are bad
contacts")
(saveDerived buttcon "Butting contacts not allowed in this design")
(drc cont
(width < 0.6) "Minimum contact size = 0.6"
)
(drc cont
(width < 1.9)
(1.9 < length) "Maximum size of contact .9 x .9"
)
(drc cont
(4 < area) "Maximum size of contact .9 x .9"
)
(drc cont
(sep < 0.6) "Minimum contact spacing = 0.6"
)
(drc diffusion noTapCon
(enc < 0.6) "Nidff, Pidff diffusion overlap contacts = 0.6"
)
(drc diffusion tapCon
(enc < 0.3) "Nidff, Pidff diffusion overlap well tap contacts =
0.3"
)
(drc cont gate
(sep < 0.6) "Nidff, Pidff diffusion contacts to poly gate = 0.6"
)
(drc poly cont
(enc < 0.3) "poly overlap contacts = 0.3"
)
(drc metal1
(width < 0.6) "Metal width = 0.6"
)
(drc metal1
(sep < 0.6) "Metal spacing = 0.6"
)
(drc metal1 cont
(enc < 0.6) "Minimum Metal overlap contacts = 0.6"
)
(Badvia = (geomAnd via cont))
(saveDerived Badvia "Via not allowed over metal-to-diffusion
contact")
(drc via
(width < 0.6) "Minimum via opening = 2"
)
(drc via
(width < 0.9)
(0.9 < length) "Max via = .9 x .9"
)
(drc via
(0.81 < area) "Max via = .9 x .9"
)
(drc via
(sep < 1.2) "Minimum via spacing = 1.2"
)
(drc poly via
(sep < 0.3) "Via to poly = 0.3"
)
(drc cont via
(sep < 0.6) "Via to contact = 0.6"
)
(drc metal1 via
(enc < 0.6) "Metal1 overlap of via = 0.6"
)
(drc metal2
(width < 0.6) "Metal2 minimum width = 0.6"
)
(drc metal2
(sep < 0.6) "Metal2 minimum spacing = 0.6"
)
(drc metal2 via
(enc < 0.6) "Metal2 overlap via = 0.6"
)
)
(ivIf
(switch "extract") then

(geomConnect
via(via cont poly metal1 psd nsd)
via(via cont sub__SD metal1)
via(via cont sub__SD_2 metal1)
via(via cont sub__SD_3 metal1)
via(via cont sub_1 metal1)
via(via cont sub_1_2 metal1)

label("v1" metal1 metal2)
label("v1" via1 metal2 metal3)
label("v1" via2 metal3 metal4)
label("v1" Ptap pwell psd metal1)
label("v1" Ntap sub nsd metal1)

label("v1" cont sub__SD_3 metal1)

)

(extractDevice pgate
(poly "G")
(psd "S" "D")
(sub "B")
"pfet ivpcell"
)


(extractDevice ngate
(poly "G")
(sub__SD_3 "S" "D")
(sub_1_2 "B")
"nfet ivpcell"
)


(wp = (measureParameter length
(pgate coincident poly) 5e-07
))
(wn = (measureParameter length
(ngate coincident poly) 5e-07
))
(lp = (measureParameter length
(pgate inside poly) 5e-07
))
(ln = (measureParameter length
(ngate inside poly) 5e-07
))
(saveParameter lp "l")
(saveParameter ln "l")
(saveParameter wp "w")
(saveParameter wn "w")

(polymetal = (measureParasitic area
(metal1 over poly) 2.8e-16 two_net
))
(polymetal2 = (measureParasitic area
(metal2 over poly not_over metal1) 2.4e-16 two_net
))
(met2met1 = (measureParasitic area
(metal2 over metal1) 2e-16 two_net
))
(saveParasitic polymetal "PLUS" "MINUS" "c"
"pcapacitor"
)
(saveParasitic polymetal2 "PLUS" "MINUS" "c"
"pcapacitor"
)
(saveParasitic met2met1 "PLUS" "MINUS" "c"
"pcapacitor"
)
(saveRecognition ngate "poly")
(saveRecognition pgate "poly")

(saveInterconnect metal1 poly pwell metal2 metal3 metal4)

)
)





And this is the report of the extraction:



\a setExtForm()
\p
\a hiFormDone(ivExtOptionsForm)
\o
\o Extraction started at Tue Feb 17 14:18:37 2004
\o
\o
\o library: FF_NO_LEAK
\o cell: VGND_FF_BALL_2
\o view: layout
\o Rules source is a simple file.
\o Rules path is /home/remol/WORK_CADENCE/divaEXT2_group.rul.
\o Inclusion limit is set to 1000.
\o Switches used: extract.
\o Running layout extraction analysis
\o flat mode
\o Full checking.
\o 50 pcapacitor parasitics created.
\o 0 pcapacitor parasitics created.
\o 0 pcapacitor parasitics created.
\o saving rep FF_NO_LEAK/VGND_FF_BALL_2/extracted
\o Extraction started.......Tue Feb 17 14:18:37 2004
\o completed ....Tue Feb 17 14:18:38 2004
\o CPU TIME = 00:00:00 TOTAL TIME = 00:00:01
\o ********* Summary of rule violation for cell "VGND_FF_BALL_2
layout" *********
\o
\o Total errors found: 0
\


















Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message
news:<np1q205lo0m2fovmgcfrbr5169avteitpk@4ax.com>...
Or that it is derived from a layer that is in geomConnect() or
geomStamp()
using something "reducing" like geomAnd() which inherits the
connectivity
(geomAnd will always return a subset of the original layer - and so is
"reducing" - geomOr() will however expand the original layer, and so
doesn't transfer connectivity).

Andrew.

On Fri, 13 Feb 2004 16:33:37 +0100, "S. Badel" <stephane.badel@epfl.ch
wrote:

that means there must be a geomConnect() or geomStamp()
statement for this layer.

dati_remo@libero.it> wrote in message
news:eddc78be.0402130703.c5082c@posting.google.com...
What means this error?

\o error: Layer 'sub_pippo_SD' must be connected.

Tahnks


o Extraction started at Fri Feb 13 15:58:09 2004
\o
\o
\o library: FF_NO_LEAK
\o cell: nhsmos4
\o view: layoutXL
\o Rules source is a simple file.
\o Rules path is /home/remol/WORK_CADENCE/divaEXT2.rul.
\o Inclusion limit is set to 1000.
\o Switches used: extract.
\o Parsing drcExtractRules of
"/home/remol/WORK_CADENCE/divaEXT2.rul"...
\o error: Layer 'sub_pippo_SD' must be connected.
\o error: Layer 'sub_pippo1' must be connected.
\o 81. extractDevice(ngate (poly "G") (sub_pippo_SD "S" "D")
(sub_pippo1 "B") "nfet ivpcell")
\o error: The saveRecognition() command must appear after
extractDevice()
\o or extractMOS() command and the first argument must be a device
recognition layer.
\o 105. saveRecognition(pgate "poly")
\o info: If short location check is desired later on, check the
saveInterconnect
\o statement for correctness:
\o Interconnect layer via, cont, psd, nsd, via1, via2, Ptap, Ntap,
sub not saved.
\o
\o Errors exist in the rules file
"/home/remol/WORK_CADENCE/divaEXT2.rul".
\o Verification program terminated.
Click to expand...
 
Thank you.

Why do you think that it looks weird?

Do you think there is a problem with their definition?

(adlvtn = (geomOr "adlvtn"))
(nplus = (geomOr "nplus"))
(active = (geomOr "active"))

(sub_1 = (geomAnd adlvtn nplus))
(sub__SD = (geomAnd sub_1 active))
(sub__SD_2 = (geomAndNot sub__SD poly))
(sub__SD_3 = (geomAnd sub__SD_2 sub__SD))
(sub_1_2 = (geomAndNot bkgnd sub__SD))


"S. Badel" <stephane.badel@epfl.ch> wrote in message news:<40324aca$1@epflnews.epfl.ch>...
your via statements look weird.
should probably be something more like

via(cont poly metal1 psd nsd)
via(cont sub__SD metal1)
via(cont sub__SD_2 metal1)
via(cont sub__SD_3 metal1)
via(cont sub_1 metal1)
via(cont sub_1_2 metal1)
via( via metal1 metal2 )
via( via1 metal2 metal3 )
via( via2 metal3 metal4 )

label statements also look weird to me.
try removing them.


dati_remo@libero.it> wrote in message
news:eddc78be.0402170524.2a4d84f5@posting.google.com...
With this divaEXT.rul file I can't extract the transistor of the
layout.


(drcExtractRules
(bkgnd = (geomBkgnd))
(pdiff = (geomOr "pdiff"))
(ndiff = (geomOr "ndiff"))
(pwell = (geomOr "pwell"))
(metal1 = (geomOr "metal1"))
(metal2 = (geomOr "metal2"))
(metal3 = (geomOr "metal3"))
(metal4 = (geomOr "metal4"))
(cont = (geomOr "contact"))
(poly = (geomOr "poly"))

(adlvtn = (geomOr "adlvtn"))
(nplus = (geomOr "nplus"))
(active = (geomOr "active"))

(sub_1 = (geomAnd adlvtn nplus))
(sub__SD = (geomAnd sub_1 active))
(sub__SD_2 = (geomAndNot sub__SD poly))
(sub__SD_3 = (geomAnd sub__SD_2 sub__SD))
(sub_1_2 = (geomAndNot bkgnd sub__SD))

(pgate = (geomAnd poly pdiff))
(ngate = (geomAnd poly ndiff))
(nsd = (geomAndNot ndiff ngate))
(psd = (geomAndNot pdiff pgate))
(via = (geomOr "v1"))
(via1 = (geomOr "v2"))
(via2 = (geomOr "v3"))
(Ptap = (geomAnd psd pwell))
(Ntap = (geomAndNot nsd pwell))
(sub = (geomAndNot bkgnd pwell))

(ivIf
(switch "do_pre") then
(measureResistance poly "lrescap" 25 0.56
"r"
(cap "c"
((1.6e-17 * a) + (2.8e-18 * p))
)
(ignore <= 0.05)
(save "y1")
(contact cont 0.03 0.5)
)
)


(ivIf
(switch "drc?") then
(drc pwell
(width < 1.8) "Minimum P- width = 1.8"
)
;;(drc pwell
;; (sep < 4.2) diffNet "P- to P- spacing = 4.2"
;;)
(drc nsd psd
(sep < 0.9) diffNet
"Ndiff to Pdiff on different nets = 0.9"
)
(badPdiff = (geomStraddle psd pwell))
(saveDerived badPdiff "Pdiff straddling Pwell")
(drc nsd pwell
(sep < 0.6) "Ndiff (substrate contact) to P-well = 0.6"
)
(drc pwell nsd
(enc < 0.6) "Ndiff (inside P-well) to P-well edge = 0.6"
)
(diffusion = (geomOr pdiff ndiff))
(drc diffusion
(width < 0.6) "Minimum Source/Drain interconnect width = 0.6"
)
(drc diffusion
(sep < 0.6) "Minimum Source/Drain spacing = 0.6"
)
(drc poly
(width < 0.6) "Minimum poly width = 0.6"
)
(drc poly
(sep < 0.6) "Minimum poly to poly spacing = 0.6"
)
(drc poly diffusion
(enc < 0.9) "Minimum gate overlap field = 0.9"
)
(gate = (geomAnd poly diffusion))
(drc diffusion gate
((0 < enc) < 1.2) opposite
"Minimum gate to diffusion edge = 1.2"
)
(drc poly diffusion
(sep < 0.3) "Minimum poly in field to edge of diffusion = 0.3"
)
(drc pimplant psd
((0 < enc) < 0.3) "P-implant overlap of S/D = 0.3"
)
(drc pimplant nsd
((0 < sep) < 0.3) "N Diff to P-implant = 0.3"
)
(drc pimplant
(sep < 0.3) "Minimum P-implant mask spacing = 0.3"
)
(drc pimplant
(notch < 0.3) "Minimum P-implant mask spacing (notch) = 3"
)
(buttcon = (geomStraddle cont ndiff))
(badcon = (geomAndNot cont
(geomCat diffusion metal1)
))
(nTapCon = (geomInside cont Ntap))
(pTapCon = (geomInside cont Ptap))
(tapCon = (geomOr nTapCon pTapCon))
(noTapCon = (geomAndNot cont tapCon))
(saveDerived badcon "Contacts not inside diffusion or metal1 are bad
contacts")
(saveDerived buttcon "Butting contacts not allowed in this design")
(drc cont
(width < 0.6) "Minimum contact size = 0.6"
)
(drc cont
(width < 1.9)
(1.9 < length) "Maximum size of contact .9 x .9"
)
(drc cont
(4 < area) "Maximum size of contact .9 x .9"
)
(drc cont
(sep < 0.6) "Minimum contact spacing = 0.6"
)
(drc diffusion noTapCon
(enc < 0.6) "Nidff, Pidff diffusion overlap contacts = 0.6"
)
(drc diffusion tapCon
(enc < 0.3) "Nidff, Pidff diffusion overlap well tap contacts =
0.3"
)
(drc cont gate
(sep < 0.6) "Nidff, Pidff diffusion contacts to poly gate = 0.6"
)
(drc poly cont
(enc < 0.3) "poly overlap contacts = 0.3"
)
(drc metal1
(width < 0.6) "Metal width = 0.6"
)
(drc metal1
(sep < 0.6) "Metal spacing = 0.6"
)
(drc metal1 cont
(enc < 0.6) "Minimum Metal overlap contacts = 0.6"
)
(Badvia = (geomAnd via cont))
(saveDerived Badvia "Via not allowed over metal-to-diffusion
contact")
(drc via
(width < 0.6) "Minimum via opening = 2"
)
(drc via
(width < 0.9)
(0.9 < length) "Max via = .9 x .9"
)
(drc via
(0.81 < area) "Max via = .9 x .9"
)
(drc via
(sep < 1.2) "Minimum via spacing = 1.2"
)
(drc poly via
(sep < 0.3) "Via to poly = 0.3"
)
(drc cont via
(sep < 0.6) "Via to contact = 0.6"
)
(drc metal1 via
(enc < 0.6) "Metal1 overlap of via = 0.6"
)
(drc metal2
(width < 0.6) "Metal2 minimum width = 0.6"
)
(drc metal2
(sep < 0.6) "Metal2 minimum spacing = 0.6"
)
(drc metal2 via
(enc < 0.6) "Metal2 overlap via = 0.6"
)
)
(ivIf
(switch "extract") then

(geomConnect
via(via cont poly metal1 psd nsd)
via(via cont sub__SD metal1)
via(via cont sub__SD_2 metal1)
via(via cont sub__SD_3 metal1)
via(via cont sub_1 metal1)
via(via cont sub_1_2 metal1)

label("v1" metal1 metal2)
label("v1" via1 metal2 metal3)
label("v1" via2 metal3 metal4)
label("v1" Ptap pwell psd metal1)
label("v1" Ntap sub nsd metal1)

label("v1" cont sub__SD_3 metal1)

)

(extractDevice pgate
(poly "G")
(psd "S" "D")
(sub "B")
"pfet ivpcell"
)


(extractDevice ngate
(poly "G")
(sub__SD_3 "S" "D")
(sub_1_2 "B")
"nfet ivpcell"
)


(wp = (measureParameter length
(pgate coincident poly) 5e-07
))
(wn = (measureParameter length
(ngate coincident poly) 5e-07
))
(lp = (measureParameter length
(pgate inside poly) 5e-07
))
(ln = (measureParameter length
(ngate inside poly) 5e-07
))
(saveParameter lp "l")
(saveParameter ln "l")
(saveParameter wp "w")
(saveParameter wn "w")

(polymetal = (measureParasitic area
(metal1 over poly) 2.8e-16 two_net
))
(polymetal2 = (measureParasitic area
(metal2 over poly not_over metal1) 2.4e-16 two_net
))
(met2met1 = (measureParasitic area
(metal2 over metal1) 2e-16 two_net
))
(saveParasitic polymetal "PLUS" "MINUS" "c"
"pcapacitor"
)
(saveParasitic polymetal2 "PLUS" "MINUS" "c"
"pcapacitor"
)
(saveParasitic met2met1 "PLUS" "MINUS" "c"
"pcapacitor"
)
(saveRecognition ngate "poly")
(saveRecognition pgate "poly")

(saveInterconnect metal1 poly pwell metal2 metal3 metal4)

)
)





And this is the report of the extraction:



\a setExtForm()
\p
\a hiFormDone(ivExtOptionsForm)
\o
\o Extraction started at Tue Feb 17 14:18:37 2004
\o
\o
\o library: FF_NO_LEAK
\o cell: VGND_FF_BALL_2
\o view: layout
\o Rules source is a simple file.
\o Rules path is /home/remol/WORK_CADENCE/divaEXT2_group.rul.
\o Inclusion limit is set to 1000.
\o Switches used: extract.
\o Running layout extraction analysis
\o flat mode
\o Full checking.
\o 50 pcapacitor parasitics created.
\o 0 pcapacitor parasitics created.
\o 0 pcapacitor parasitics created.
\o saving rep FF_NO_LEAK/VGND_FF_BALL_2/extracted
\o Extraction started.......Tue Feb 17 14:18:37 2004
\o completed ....Tue Feb 17 14:18:38 2004
\o CPU TIME = 00:00:00 TOTAL TIME = 00:00:01
\o ********* Summary of rule violation for cell "VGND_FF_BALL_2
layout" *********
\o
\o Total errors found: 0
\


















Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message
news:<np1q205lo0m2fovmgcfrbr5169avteitpk@4ax.com>...
Or that it is derived from a layer that is in geomConnect() or
geomStamp()
using something "reducing" like geomAnd() which inherits the
connectivity
(geomAnd will always return a subset of the original layer - and so is
"reducing" - geomOr() will however expand the original layer, and so
doesn't transfer connectivity).

Andrew.

On Fri, 13 Feb 2004 16:33:37 +0100, "S. Badel" <stephane.badel@epfl.ch
wrote:

that means there must be a geomConnect() or geomStamp()
statement for this layer.

dati_remo@libero.it> wrote in message
news:eddc78be.0402130703.c5082c@posting.google.com...
What means this error?

\o error: Layer 'sub_pippo_SD' must be connected.

Tahnks


o Extraction started at Fri Feb 13 15:58:09 2004
\o
\o
\o library: FF_NO_LEAK
\o cell: nhsmos4
\o view: layoutXL
\o Rules source is a simple file.
\o Rules path is /home/remol/WORK_CADENCE/divaEXT2.rul.
\o Inclusion limit is set to 1000.
\o Switches used: extract.
\o Parsing drcExtractRules of
"/home/remol/WORK_CADENCE/divaEXT2.rul"...
\o error: Layer 'sub_pippo_SD' must be connected.
\o error: Layer 'sub_pippo1' must be connected.
\o 81. extractDevice(ngate (poly "G") (sub_pippo_SD "S" "D")
(sub_pippo1 "B") "nfet ivpcell")
\o error: The saveRecognition() command must appear after
extractDevice()
\o or extractMOS() command and the first argument must be a device
recognition layer.
\o 105. saveRecognition(pgate "poly")
\o info: If short location check is desired later on, check the
saveInterconnect
\o statement for correctness:
\o Interconnect layer via, cont, psd, nsd, via1, via2, Ptap, Ntap,
sub not saved.
\o
\o Errors exist in the rules file
"/home/remol/WORK_CADENCE/divaEXT2.rul".
\o Verification program terminated.
Click to expand...
 
in a correct statement, the first layer is the via and the rest
is the layers to be connected through this via.

in you car, the line

via(via cont poly metal1 psd nsd)

suggest that the via layer is connecting cont, poly, met1
and diffusion toghether, which is obviously not the wanted
effect. also there is no via connecting to met2, met3 or met4.

the label statement should look like label( metal1 metal1 )
which means that text on metal1 layer applies to metal1 shapes.

try it, we'll see


<dati_remo@libero.it> wrote in message
news:eddc78be.0402180223.25a0df3a@posting.google.com...
Thank you.

Why do you think that it looks weird?

Do you think there is a problem with their definition?

(adlvtn = (geomOr "adlvtn"))
(nplus = (geomOr "nplus"))
(active = (geomOr "active"))

(sub_1 = (geomAnd adlvtn nplus))
(sub__SD = (geomAnd sub_1 active))
(sub__SD_2 = (geomAndNot sub__SD poly))
(sub__SD_3 = (geomAnd sub__SD_2 sub__SD))
(sub_1_2 = (geomAndNot bkgnd sub__SD))


"S. Badel" <stephane.badel@epfl.ch> wrote in message
news:<40324aca$1@epflnews.epfl.ch>...
your via statements look weird.
should probably be something more like

via(cont poly metal1 psd nsd)
via(cont sub__SD metal1)
via(cont sub__SD_2 metal1)
via(cont sub__SD_3 metal1)
via(cont sub_1 metal1)
via(cont sub_1_2 metal1)
via( via metal1 metal2 )
via( via1 metal2 metal3 )
via( via2 metal3 metal4 )

label statements also look weird to me.
try removing them.


dati_remo@libero.it> wrote in message
news:eddc78be.0402170524.2a4d84f5@posting.google.com...
With this divaEXT.rul file I can't extract the transistor of the
layout.


(drcExtractRules
(bkgnd = (geomBkgnd))
(pdiff = (geomOr "pdiff"))
(ndiff = (geomOr "ndiff"))
(pwell = (geomOr "pwell"))
(metal1 = (geomOr "metal1"))
(metal2 = (geomOr "metal2"))
(metal3 = (geomOr "metal3"))
(metal4 = (geomOr "metal4"))
(cont = (geomOr "contact"))
(poly = (geomOr "poly"))

(adlvtn = (geomOr "adlvtn"))
(nplus = (geomOr "nplus"))
(active = (geomOr "active"))

(sub_1 = (geomAnd adlvtn nplus))
(sub__SD = (geomAnd sub_1 active))
(sub__SD_2 = (geomAndNot sub__SD poly))
(sub__SD_3 = (geomAnd sub__SD_2 sub__SD))
(sub_1_2 = (geomAndNot bkgnd sub__SD))

(pgate = (geomAnd poly pdiff))
(ngate = (geomAnd poly ndiff))
(nsd = (geomAndNot ndiff ngate))
(psd = (geomAndNot pdiff pgate))
(via = (geomOr "v1"))
(via1 = (geomOr "v2"))
(via2 = (geomOr "v3"))
(Ptap = (geomAnd psd pwell))
(Ntap = (geomAndNot nsd pwell))
(sub = (geomAndNot bkgnd pwell))

(ivIf
(switch "do_pre") then
(measureResistance poly "lrescap" 25 0.56
"r"
(cap "c"
((1.6e-17 * a) + (2.8e-18 * p))
)
(ignore <= 0.05)
(save "y1")
(contact cont 0.03 0.5)
)
)


(ivIf
(switch "drc?") then
(drc pwell
(width < 1.8) "Minimum P- width = 1.8"
)
;;(drc pwell
;; (sep < 4.2) diffNet "P- to P- spacing = 4.2"
;;)
(drc nsd psd
(sep < 0.9) diffNet
"Ndiff to Pdiff on different nets = 0.9"
)
(badPdiff = (geomStraddle psd pwell))
(saveDerived badPdiff "Pdiff straddling Pwell")
(drc nsd pwell
(sep < 0.6) "Ndiff (substrate contact) to P-well = 0.6"
)
(drc pwell nsd
(enc < 0.6) "Ndiff (inside P-well) to P-well edge = 0.6"
)
(diffusion = (geomOr pdiff ndiff))
(drc diffusion
(width < 0.6) "Minimum Source/Drain interconnect width = 0.6"
)
(drc diffusion
(sep < 0.6) "Minimum Source/Drain spacing = 0.6"
)
(drc poly
(width < 0.6) "Minimum poly width = 0.6"
)
(drc poly
(sep < 0.6) "Minimum poly to poly spacing = 0.6"
)
(drc poly diffusion
(enc < 0.9) "Minimum gate overlap field = 0.9"
)
(gate = (geomAnd poly diffusion))
(drc diffusion gate
((0 < enc) < 1.2) opposite
"Minimum gate to diffusion edge = 1.2"
)
(drc poly diffusion
(sep < 0.3) "Minimum poly in field to edge of diffusion = 0.3"
)
(drc pimplant psd
((0 < enc) < 0.3) "P-implant overlap of S/D = 0.3"
)
(drc pimplant nsd
((0 < sep) < 0.3) "N Diff to P-implant = 0.3"
)
(drc pimplant
(sep < 0.3) "Minimum P-implant mask spacing = 0.3"
)
(drc pimplant
(notch < 0.3) "Minimum P-implant mask spacing (notch) = 3"
)
(buttcon = (geomStraddle cont ndiff))
(badcon = (geomAndNot cont
(geomCat diffusion metal1)
))
(nTapCon = (geomInside cont Ntap))
(pTapCon = (geomInside cont Ptap))
(tapCon = (geomOr nTapCon pTapCon))
(noTapCon = (geomAndNot cont tapCon))
(saveDerived badcon "Contacts not inside diffusion or metal1 are bad
contacts")
(saveDerived buttcon "Butting contacts not allowed in this design")
(drc cont
(width < 0.6) "Minimum contact size = 0.6"
)
(drc cont
(width < 1.9)
(1.9 < length) "Maximum size of contact .9 x .9"
)
(drc cont
(4 < area) "Maximum size of contact .9 x .9"
)
(drc cont
(sep < 0.6) "Minimum contact spacing = 0.6"
)
(drc diffusion noTapCon
(enc < 0.6) "Nidff, Pidff diffusion overlap contacts = 0.6"
)
(drc diffusion tapCon
(enc < 0.3) "Nidff, Pidff diffusion overlap well tap contacts =
0.3"
)
(drc cont gate
(sep < 0.6) "Nidff, Pidff diffusion contacts to poly gate = 0.6"
)
(drc poly cont
(enc < 0.3) "poly overlap contacts = 0.3"
)
(drc metal1
(width < 0.6) "Metal width = 0.6"
)
(drc metal1
(sep < 0.6) "Metal spacing = 0.6"
)
(drc metal1 cont
(enc < 0.6) "Minimum Metal overlap contacts = 0.6"
)
(Badvia = (geomAnd via cont))
(saveDerived Badvia "Via not allowed over metal-to-diffusion
contact")
(drc via
(width < 0.6) "Minimum via opening = 2"
)
(drc via
(width < 0.9)
(0.9 < length) "Max via = .9 x .9"
)
(drc via
(0.81 < area) "Max via = .9 x .9"
)
(drc via
(sep < 1.2) "Minimum via spacing = 1.2"
)
(drc poly via
(sep < 0.3) "Via to poly = 0.3"
)
(drc cont via
(sep < 0.6) "Via to contact = 0.6"
)
(drc metal1 via
(enc < 0.6) "Metal1 overlap of via = 0.6"
)
(drc metal2
(width < 0.6) "Metal2 minimum width = 0.6"
)
(drc metal2
(sep < 0.6) "Metal2 minimum spacing = 0.6"
)
(drc metal2 via
(enc < 0.6) "Metal2 overlap via = 0.6"
)
)
(ivIf
(switch "extract") then

(geomConnect
via(via cont poly metal1 psd nsd)
via(via cont sub__SD metal1)
via(via cont sub__SD_2 metal1)
via(via cont sub__SD_3 metal1)
via(via cont sub_1 metal1)
via(via cont sub_1_2 metal1)

label("v1" metal1 metal2)
label("v1" via1 metal2 metal3)
label("v1" via2 metal3 metal4)
label("v1" Ptap pwell psd metal1)
label("v1" Ntap sub nsd metal1)

label("v1" cont sub__SD_3 metal1)

)

(extractDevice pgate
(poly "G")
(psd "S" "D")
(sub "B")
"pfet ivpcell"
)


(extractDevice ngate
(poly "G")
(sub__SD_3 "S" "D")
(sub_1_2 "B")
"nfet ivpcell"
)


(wp = (measureParameter length
(pgate coincident poly) 5e-07
))
(wn = (measureParameter length
(ngate coincident poly) 5e-07
))
(lp = (measureParameter length
(pgate inside poly) 5e-07
))
(ln = (measureParameter length
(ngate inside poly) 5e-07
))
(saveParameter lp "l")
(saveParameter ln "l")
(saveParameter wp "w")
(saveParameter wn "w")

(polymetal = (measureParasitic area
(metal1 over poly) 2.8e-16 two_net
))
(polymetal2 = (measureParasitic area
(metal2 over poly not_over metal1) 2.4e-16 two_net
))
(met2met1 = (measureParasitic area
(metal2 over metal1) 2e-16 two_net
))
(saveParasitic polymetal "PLUS" "MINUS" "c"
"pcapacitor"
)
(saveParasitic polymetal2 "PLUS" "MINUS" "c"
"pcapacitor"
)
(saveParasitic met2met1 "PLUS" "MINUS" "c"
"pcapacitor"
)
(saveRecognition ngate "poly")
(saveRecognition pgate "poly")

(saveInterconnect metal1 poly pwell metal2 metal3 metal4)

)
)





And this is the report of the extraction:



\a setExtForm()
\p
\a hiFormDone(ivExtOptionsForm)
\o
\o Extraction started at Tue Feb 17 14:18:37 2004
\o
\o
\o library: FF_NO_LEAK
\o cell: VGND_FF_BALL_2
\o view: layout
\o Rules source is a simple file.
\o Rules path is /home/remol/WORK_CADENCE/divaEXT2_group.rul.
\o Inclusion limit is set to 1000.
\o Switches used: extract.
\o Running layout extraction analysis
\o flat mode
\o Full checking.
\o 50 pcapacitor parasitics created.
\o 0 pcapacitor parasitics created.
\o 0 pcapacitor parasitics created.
\o saving rep FF_NO_LEAK/VGND_FF_BALL_2/extracted
\o Extraction started.......Tue Feb 17 14:18:37 2004
\o completed ....Tue Feb 17 14:18:38 2004
\o CPU TIME = 00:00:00 TOTAL TIME = 00:00:01
\o ********* Summary of rule violation for cell "VGND_FF_BALL_2
layout" *********
\o
\o Total errors found: 0
\


















Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message
news:<np1q205lo0m2fovmgcfrbr5169avteitpk@4ax.com>...
Or that it is derived from a layer that is in geomConnect() or
geomStamp()
using something "reducing" like geomAnd() which inherits the
connectivity
(geomAnd will always return a subset of the original layer - and so
is
"reducing" - geomOr() will however expand the original layer, and so
doesn't transfer connectivity).

Andrew.

On Fri, 13 Feb 2004 16:33:37 +0100, "S. Badel"
stephane.badel@epfl.ch
wrote:

that means there must be a geomConnect() or geomStamp()
statement for this layer.

dati_remo@libero.it> wrote in message
news:eddc78be.0402130703.c5082c@posting.google.com...
What means this error?

\o error: Layer 'sub_pippo_SD' must be connected.

Tahnks


o Extraction started at Fri Feb 13 15:58:09 2004
\o
\o
\o library: FF_NO_LEAK
\o cell: nhsmos4
\o view: layoutXL
\o Rules source is a simple file.
\o Rules path is /home/remol/WORK_CADENCE/divaEXT2.rul.
\o Inclusion limit is set to 1000.
\o Switches used: extract.
\o Parsing drcExtractRules of
"/home/remol/WORK_CADENCE/divaEXT2.rul"...
\o error: Layer 'sub_pippo_SD' must be connected.
\o error: Layer 'sub_pippo1' must be connected.
\o 81. extractDevice(ngate (poly "G") (sub_pippo_SD "S" "D")
(sub_pippo1 "B") "nfet ivpcell")
\o error: The saveRecognition() command must appear after
extractDevice()
\o or extractMOS() command and the first argument must be a
device
recognition layer.
\o 105. saveRecognition(pgate "poly")
\o info: If short location check is desired later on, check the
saveInterconnect
\o statement for correctness:
\o Interconnect layer via, cont, psd, nsd, via1, via2, Ptap,
Ntap,
sub not saved.
\o
\o Errors exist in the rules file
"/home/remol/WORK_CADENCE/divaEXT2.rul".
\o Verification program terminated.
Click to expand...
 
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