Extracting wire parasitic from silicon ensemble or other too

[nimayshah]

Hi all,

I am using silicon ensemble for automatic place and route of some
iscas '85 benchmarks and then exporting the designs in gds2 format
which are then streamed (imported) into icfb (virtuoso). Then i have
to extract the spice netlist from the layout and run some simulations
on them using hspice. I also have to consider wire parasitics. I have
the following questions:
Is there anyway by which i can automate this by silicon ensemble or
any other tool?
If this cannot be automated what is the best method to use, which is
easily scalable (equally easy to apply on large benchmarks) by which i
can put in the wire parasitics in my spice file?
Also, i have one more question, which is not related to this, but what
exactly is the .dspf file which we can get from silicon ensemble?

Thanks,

Regards,

Nimay Shah

 

[gerry@ictooling.com]

On Feb 13, 3:53 am, "nimayshah" <nimays...@gmail.com> wrote:

Hi all,

I am using silicon ensemble for automatic place and route of some
iscas '85 benchmarks and then exporting the designs in gds2 format
which are then streamed (imported) into icfb (virtuoso). Then i have
to extract the spice netlist from the layout and run some simulations
on them using hspice. I also have to consider wire parasitics. I have
the following questions:
Is there anyway by which i can automate this by silicon ensemble or
any other tool?

This depends on what parasitics you would like to extract.

If this cannot be automated what is the best method to use, which is
easily scalable (equally easy to apply on large benchmarks) by which i
can put in the wire parasitics in my spice file?

Trivial simplified parasitics can be extracted using many existing
flows.

Also, i have one more question, which is not related to this, but what
exactly is the .dspf file which we can get from silicon ensemble?

DSPF is a "Detailed Standard Parasitic File"

It will show you some standard parasitic (capacitance) numbers about
each "detailed" wire section.

If you only require some first order (Capacitance )effects, then this
will show you the way.

If you require High Frequency Characteristics, then this method will
only get you
so far.

Since you are talking about a P&R design, then we can assume that you
have models
for the Cells. These cell models have made several assumptions about
edge rates and
power requirements and drive impedance. These things will set your max
accuracy
even if you got "IDEAL" interconnect modeling, so you need to
understand this limit and
then create your parasitic interconnect files with this in mind.

So ... it would be silly to have interconnect modeling that handled
advanced things like
shielding/side capacitance/self inductance/Resistance/ Freq effects/
Mutual Inductance/
substrate effects ... 3D modeling ... etc. on your wiring, when the
accuracy of your models only requires lumped-to-ground Capacitance ...

Then again ... when in the Analog ... +20GHz .. DSM area ... you need
to understand
what is significant ...

Sorry if this is no help, but Parasitics are always an aproximation
and you should always
only attempt to generate significant ones.

YMMV
-- Gerry