Extracted view doesn't recognize global nets

[Dmitriy Shurin]

Hi!
I try to run a simle not gate simulation. The problem is that the
simulation for schematic view runs just fine, but simulation for
extracted view doesn't run well: the results i get are like there wasn't
power supply present. I've checked the netlist for schematic and
extracted views and found out that in netlist for schematic view global
nets (vdd! and gnd!) appear and for extracted view net0 and net1 appear
instead. What is the problem that causes global nets to disappear?
P.S.: I use Cadence v. 5.0.0 sub-version 5.0.33_USR2.34.8. The kit i
work with is tsmc 0.18u.


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[S. Badel]

similar problem was encountered with ams design kit.
the workaround involved running a few commands on the CIW after extraction.

cv = geGetEditCellView()
auLvsMakeGlobals(cv)
auLvsFixTimeStamps(cv)
dbSave(cv)

maybe the same is happening to you ?

stéphane





Dmitriy Shurin wrote:

Hi!
I try to run a simle not gate simulation. The problem is that the
simulation for schematic view runs just fine, but simulation for
extracted view doesn't run well: the results i get are like there wasn't
power supply present. I've checked the netlist for schematic and
extracted views and found out that in netlist for schematic view global
nets (vdd! and gnd!) appear and for extracted view net0 and net1 appear
instead. What is the problem that causes global nets to disappear?
P.S.: I use Cadence v. 5.0.0 sub-version 5.0.33_USR2.34.8. The kit i
work with is tsmc 0.18u.

 

[meghna]

To solve it out, open your LVS form. There is an option 'build analog'.
Click on it. Then a new view named 'analog_extracted' will be
automatically saved. Now open your schematic and its analog design
enviornment window. Go to-
Setup-->Environment-->Switch View List, type analog_extracted (as first
view)

Hope it will work.